RayBench EmbeddedInteractive engineering labs
ARCHITECTURE

Architecture

Architecture from reset to reliable products: bootloaders and firmware recovery, Arm Cortex-M/A/R, NVIC, RISC-V, AVR, 8051, and a live Cortex-M0 lab.

Interactive lab

This page is a live simulation rather than a written lesson: enable JavaScript to use its controls, visualizations, and code traces. The written lessons for this subject are linked below.

More in Architecture

  • ARM Assembly LabA working ARM Cortex-M0 assembler and CPU emulator in the browser: real Thumb encodings, N/Z/C/V flags, memory-mapped LEDs/UART/timer, NVIC exception stacking, and graded assembly challenges with automated checking.
  • Cortex-MArm Cortex-M programmers model, Thumb-2 ISA, memory-mapped peripherals, and NVIC interrupt handling. Interactive register and stack simulator.
  • BootLab 0 → 100Design a reliable bootloader and firmware-update system from reset handoff and flash geometry through image authentication, A/B slots, atomic metadata, trial boot, rollback, recovery, and exhaustive power-cut injection.
  • NVICNVIC for Cortex-M: priority levels, tail-chaining, late-arrival, and vector table. Interactive lab for interrupt latency and preemption.
  • How to Read Any CPUThe six questions that pin down any processor's contract with software: registers, PC and stack, status flags, load/store or memory operands, exception entry, and the memory model. Asked once in the abstract, then answered by every architecture in this section.
  • 8051 / MCS-518051/MCS-51 simulator: 4 register banks, SFR map, bit-addressable RAM, and MOV/CJNE/DJNZ instructions. Observe accumulator and PSW flags.
  • Cortex-AArm Cortex-A model: MMU page tables, exception levels EL0-EL3, and GIC. Interactive simulator for virtual memory translation.
  • AVRAVR architecture: Harvard 8-bit RISC, 32 general-purpose registers, SRAM, and EEPROM. Interactive register and memory access lab.
  • Assembly Across ISAsAssembly for Arm Thumb, RISC-V, AVR, and 8051: mnemonics, addressing modes, and stack frames. Interactive assembler/disassembler.
  • Cortex-RArm Cortex-R real-time core: MPU regions, tightly-coupled memory, and dual-core lockstep. Interactive MPU configuration lab.
  • Architecture MapInteractive architecture map comparing Arm Cortex-M/A/R, RISC-V, AVR, and 8051 ISA, memory maps, and interrupt models.
  • RISC-VRISC-V ISA: RV32I/RV64I base integer set, M/S/U privilege levels, and CSR registers. Interactive instruction execution simulator.