Understand the machine, not just the answer.

How RayBench teaches

Each lesson moves from intuition to definitions, derivations, worked examples, simulation, complete implementation, edge cases, and independent practice. The interactive controls sit alongside the text rather than replacing it, so the reasoning behind a result is always readable.

Embedded DSA

• Sorting Under ConstraintLearn nine sorting algorithms with record-by-record traces: insertion, selection, bubble, Shell, merge, quick, heap, counting and radix. Compare stability, temporary storage and input-dependent work, then solve the C11 firmware exercises.
• Arrays & WindowsTwo pointers, sliding windows, in-place compaction and streaming filters over sample buffers. Twelve problems with complete C11 solutions, complexity targets and edge-case tests.
• Search & LookupBinary search that actually terminates, lookup tables, perfect hashing and command dispatch. Eleven problems on getting a bounded answer out of a table without a heap allocation in sight.
• Lists, Pools & ArenasFollow packet storage through allocation, use and release. Compare fixed-block pools, linked lists and arenas, including exhaustion, lifetime and allocation trade-offs.
• Trees, Graphs & StateTries for command tables, union-find for connectivity, and state machines that cannot reach an undefined state. Nine problems on structures that encode relationships rather than sequences.
• Parsing & ProtocolsFraming, COBS, incremental parsers and adversarial input. Nine problems on decoding a byte stream from a hostile world without a buffer overflow or an unbounded loop.
• Change the order by changing linksEvery list variant, written for embedded C rather than for a whiteboard: singly and doubly linked, circular lists and sentinels that delete the boundary cases, the intrusive form kernels and firmware actually use, static pools and free lists for systems without malloc, reversal and cycle detection, and an honest account of when an array is the better answer.
• Practice one explanation at a timeA complete embedded-first DSA course with theory, 80 challenges, complete C11 implementations, visual traces, mastery tracking, interview drills, and a constraint-driven firmware design arena.
• Heaps & SchedulingInsert and remove deadlines in a binary min-heap, then study scheduling and wrapping tick counters. Heaps and timer wheels are different timer-management structures.
• Stacks, Queues & RingsThe ring buffer and the SPSC queue: the two structures every firmware project actually ships. Ownership between an ISR and a main loop, overflow policy, and why the full/empty test is where the bugs are.
• Bits & BytesRegister fields, bit reversal, parity, endianness and portable packet decoding, without invoking undefined behaviour. Seven problems with complete C11 solutions and a step-by-step trace for each.
• Integer & Fixed-Point MathComputing the right number with no floating-point unit. Q formats, multiply-before-divide, rounding instead of truncating, division by a constant as a multiply and shift, running averages that do not stall, and LFSR jitter for backoff.

CMOS & VLSI

• Silicon Foundations & MOS PhysicsSemiconductor foundations, pn junctions, MOS electrostatics, NMOS/PMOS operation, compact models, and scaled-device nonidealities.
• Reliability, Layout & SignoffESD, latch-up, back-powering, stick diagrams, layout, DRC/LVS/PEX, PVT, characterization, constraints, and STA.
• Timing, Interconnect & PowerRC delay, slew, logical effort, wire models, coupling, repeaters, dynamic and short-circuit power, leakage, and glitches.
• MOSFET DerivationsWhere the formulae come from: the gradual-channel integration, threshold and body effect, small-signal parameters, and the subthreshold floor.
• Dynamic CMOS & DominoPrecharge and evaluate, domino cascading, charge sharing and keepers - the fast logic family, and the honest account of why it faded.
• The Real Four-Terminal MOSFETThe device you actually get: four terminals, body diodes, five gate capacitances that move with operating region, series resistance and temperature.
• CMOS Anatomy & Cross-SectionWhat the silicon actually looks like: wells, diffusions, STI, the gate stack, contacts and taps - and why an inverter needs all of it.
• The FET FamilyEvery field-effect device on one map: junction, Schottky, insulated and heterojunction gates, and the geometry answers - FinFET, GAAFET and power devices.
• The CMOS InverterVTC regions, switching threshold, noise margins, ratioing, sizing, load capacitance, transition behavior, and measurement.
• Static CMOS, Complex Gates & Pass LogicPull-up/pull-down duality, NAND/NOR/AOI/OAI sizing, transmission gates, degraded levels, hazards, and transistor-level inspection.
• Sequential Logic, Metastability & CDCLatches, flip-flops, setup/hold, clocking, metastability, synchronizers, handshakes, pulse and multi-bit crossings.

Embedded C

• Structs, Unions, Enums & TypedefStructs, unions, enums, typedef aliases, bit-fields, designated initialization, tagged variants, and opaque handles.
• Embedded C and Firmware SystemsDiagnostics, focused C practice, contextual DSA bridges, compiled examples, production projects, and design-defense prompts.
• Types, Promotion & ArithmeticInteger widths, signedness, promotion, conversions, overflow, qualifiers, floating point, size, and alignment.
• MMIO, Volatile & Access SemanticsMemory-mapped I/O, volatile guarantees, read and write side effects, read-modify-write hazards, barriers, and assembly evidence.
• Functions, Modules & ContractsFunction declarations, parameters, callbacks, linkage, reentrancy, error contracts, opaque modules, HAL seams, and failure states.
• Interrupts, Atomicity & PublicationInterrupt context, latency, shared state, atomic width, critical sections, ordering, publication, and deferred work.
• Compiler WorkbenchEdit C, compile for embedded targets, inspect diagnostics, assembly, sections, symbols, code size, and run a host-side test harness.
• Bits, Fields, Endianness & EncodingsSafe mask construction, field extraction and insertion, shifts, Gray code, endianness, packing, and representation boundaries.
• State Machines, Dispatch & TimeoutsExplicit state, events, transition tables, function-pointer dispatch, timers, timeouts, invalid states, and exhaustive tests.

Micro & Nano

• Semiconductor Devices 1Derive carrier populations and transport, then connect electrostatics to diodes, BJT and MOS devices.
• Materials of Micro- and NanotechnologiesConnect bonding and structure to transport, growth, compatibility and device behaviour.
• Electronics Technology 1How requirements become a manufactured, measurable and reliable electronic assembly.
• How a wafer becomes a functioning deviceSemiconductor fabrication and cleanroom technology: silicon wafers, RCA cleaning, oxidation, lithography, etching, doping, PVD/CVD/ALD, metallization, CMP, packaging, test and the complete CMOS flow from sand to transistor.
• NanodiagnosticsFollow excitation through sample interaction and detection to a defensible material conclusion.
• NanotechnologyWhy size changes behaviour, and how nanostructures are patterned, grown and integrated.

Foundations

• Pointers & Memory SafetyAddresses, dereferencing, arrays, pointer arithmetic, ownership and invalid accesses.
• Computer Systems from First PrinciplesCPU, memory, storage, buses, instructions and the performance of the complete system.
• Cache Coherency and Memory OrderingMESI, ownership, ordering, atomics, DMA and false sharing.

Architecture

• Microcontroller Assembly LabA working ARM Cortex-M0 assembler and CPU emulator in the browser: real Thumb encodings, N/Z/C/V flags, memory-mapped LEDs/UART/timer, NVIC exception stacking, and graded assembly challenges with automated checking.
• Cortex-MArm Cortex-M programmers model, Thumb-2 ISA, memory-mapped peripherals, and NVIC interrupt handling. Interactive register and stack simulator.

Connectivity

• CAN BusCAN bus arbitration, dominant/recessive voltage levels, bit stuffing, frame structure, and error states. Interactive multi-node arbitration simulator, a full-frame walkthrough that animates every field (SOF, ID, DLC, data, CRC-15, ACK, EOF) on real CANH/CANL voltage waveforms, a CRC noise demo, and a fault-injection debug lab.
• SPISPI bus modes (CPOL/CPHA), clock polarity, phase, and multi-slave chip-select. Interactive lab for MOSI/MISO timing.

DSP

• Camera Engineering from Sensor to ImageComplete camera engineering from optics, CMOS pixels, exposure and RAW formats through MIPI CSI-2, UVC, machine-vision interfaces, ISP/DSP, DMA, V4L2, debugging, code and interview preparation.