CMOS & VLSI

CMOS Anatomy & Cross-Section

What the silicon actually looks like: wells, diffusions, STI, the gate stack, contacts and taps - and why an inverter needs all of it.

Reviewed 2026-08-223,446 words

1. One transistor, from substrate to metal

Draw a lightly doped p-type substrate. Into its surface, implant two heavily doped n-type regions a short distance apart - these are the source and drain, and the gap between them is the channel. Grow a very thin oxide over that gap, and put a conductive gate on top of it. That is a complete NMOS transistor: four regions, one insulator, one electrode. Everything derived about drain current describes charge moving in the gap between those two implants, controlled by a plate sitting a couple of nanometres above it.

The details that surround it are all there to make that structure usable. Shallow trench isolation is an etched trench refilled with oxide, and it separates each device from its neighbours - without it, two adjacent diffusions in the same substrate are simply a resistor. Silicide is a metal-silicon compound formed on top of the source, drain and gate to cut their sheet resistance, because doped silicon is a poor conductor by wiring standards. Contacts are tungsten plugs that connect those silicided regions up to the first metal layer, and vias connect one metal layer to the next.

The gate itself has changed twice in the industry's history and the names stuck. Early devices used a metal gate over oxide, which is where the M and O in MOSFET come from. That was replaced by doped polysilicon, which could be deposited after the source and drain were defined and so allowed the gate to self-align to them - a decisive manufacturing advantage. Modern nodes went back to metal, paired with a high-permittivity dielectric instead of silicon dioxide, because an oxide thin enough for the required capacitance had become thin enough to tunnel through. The acronym now describes none of the materials.

First-order relation

C_{ox} = \frac{\varepsilon_{ox}}{t_{ox}} = \frac{k\,\varepsilon_0}{t_{ox}}

Derivation: Show why a high-k dielectric lets the oxide get physically thicker without losing gate control.

The gate stack behaves as a parallel-plate capacitor, so capacitance depends only on permittivity and thickness.
Electrostatic control of the channel depends on capacitance per unit area, not on the physical thickness itself.
Gate tunnelling current falls roughly exponentially with physical barrier thickness.

C_{ox} = \frac{k\,\varepsilon_0}{t} - Parallel-plate capacitance per unit area, with k the relative permittivity of whatever dielectric is used.
\frac{k_1}{t_1} = \frac{k_2}{t_2} - Require the same capacitance per unit area from the two materials, since that is what sets channel charge per volt.
t_2 = t_1\,\frac{k_2}{k_1} - Rearrange. A material with five times the permittivity may be five times thicker for identical electrostatics.
EOT = t_2\,\frac{k_{ox}}{k_2} - Define equivalent oxide thickness: the silicon-dioxide thickness that would give the same capacitance, which is how datasheets quote it.
J_{gate} \propto e^{-\alpha t} - Tunnelling probability falls exponentially with barrier thickness, so the extra physical thickness is worth orders of magnitude of gate leakage.

Capacitance depends on the ratio of permittivity to thickness while tunnelling depends on thickness alone. Raising the permittivity decouples the two, which is the entire reason for the high-k transition.

Gate capacitance: C_{ox} = \frac{k\,\varepsilon_0}{t_{ox}} - Per unit area. The reason a thinner oxide, or a higher k, buys more channel charge per volt.
Equivalent oxide thickness: EOT = t_{high\text{-}k}\,\frac{k_{ox}}{k_{high\text{-}k}} - How thick the layer would have to be in silicon dioxide for the same capacitance.
Sheet resistance: R_{sheet} = \frac{\rho}{t} - Ohms per square. Why silicide exists: doped silicon alone is far too resistive to wire with.
Contact resistance: R_{total} = R_{sheet}\frac{L}{W} + 2R_{contact} - At small dimensions the contact term dominates, which is why contacts are multiplied rather than enlarged.

A 2 nm silicon dioxide layer with k = 3.9 gives C_ox = 3.9 x 8.854e-12 / 2e-9, about 17.3 mF/m^2 or 1.73 uF/cm^2. Replacing it with hafnium dioxide at k = 20 and the same capacitance allows a physical thickness of 2 x (20/3.9), about 10.3 nm - five times thicker for the same electrostatic control, which is exactly the point. Gate tunnelling current falls roughly exponentially with physical thickness, so that swap bought several orders of magnitude of gate leakage back.

The letters in MOSFET stand for metal-oxide-semiconductor. On a modern node, how many of those three materials are actually present as described?

The metal is back, after decades of polysilicon gates, so that one is accurate again. The oxide usually is not - it is a high-permittivity dielectric such as hafnium oxide, chosen because a silicon dioxide layer thin enough to give the same capacitance would leak by tunnelling. The semiconductor is still silicon. The name records the 1960s structure rather than the current one.

2. The complementary pair: wells, and why the bodies go to opposite rails

An NMOS needs a p-type body. A PMOS needs an n-type body. They cannot both sit directly in the same substrate, so one of them is given a tub of the opposite type to live in. On a p-type substrate, the PMOS devices sit inside an n-well; on an n-type substrate it is the other way round; a twin-well process implants both explicitly so each device type gets a body doping chosen for its own threshold rather than inheriting whatever the wafer happened to be. That is the whole structural difference between an NMOS and a PMOS on a die - the same gate stack over an oppositely doped tub, with oppositely doped diffusions.

The bodies are then tied to opposite rails, and the reason is the same for both: every source and drain diffusion forms a pn junction with the body around it, and those junctions must stay reverse biased. An NMOS body goes to ground because its n-type diffusions sit in p-type material and ground is the lowest potential in the circuit, so the junctions can never forward bias. A PMOS n-well goes to the supply for the mirror-image reason. Get either one wrong and the junction conducts: the transistor stops being a switch and becomes a diode to the substrate.

There is a second, sharper reason. The n-well, p-substrate and the diffusions inside them form parasitic bipolar transistors that are cross-coupled into a structure equivalent to a thyristor. If enough current is injected into the substrate - by a supply overshoot, an input driven beyond a rail, or an ESD event - that structure can latch into a low-impedance path from supply to ground and stay there until the power is removed, usually destroying the chip. Latch-up is the name, and holding both bodies firmly at their rails through low-resistance connections is the primary defence.

First-order relation

V_{SB,nmos} \ge 0,\qquad V_{BS,pmos} \ge 0

Derivation: Show why body ties are placed repeatedly across a die rather than once per well.

The substrate and well are resistive, not equipotential - they are lightly doped silicon, not metal.
Injected current flows laterally through that resistance to the nearest tap.
The parasitic bipolar turns on when its base-emitter junction reaches roughly 0.6 V.

R_{sub} = R_{sheet}\,\frac{d}{w} - The resistance from an injection point to a tap grows with distance, because the substrate is a distributed resistor.
V_{local} = I_{inj}\,R_{sub} - Ohm's law: injected current flowing to a distant tap develops a local potential where it was injected.
V_{local} \ge 0.6\ \mathrm{V} \Rightarrow \text{parasitic BJT conducts} - That local rise forward biases the base-emitter junction of the parasitic bipolar, turning it on.
\beta_{npn}\beta_{pnp} > 1 \Rightarrow \text{latch} - Once both parasitic transistors conduct, their cross-coupled loop gain exceeding one makes the state self-sustaining.
d \downarrow \Rightarrow R_{sub}\downarrow \Rightarrow V_{local}\downarrow - Shortening the distance to the nearest tap reduces the resistance and so the local potential rise, for the same injected current.

Taps are repeated across the die because the defence is resistive, not topological. It is not enough for the well to be connected somewhere - it must be connected near every device, so that injected current cannot develop 0.6 V anywhere.

Junction reverse bias: V_{D} > V_{B}\ (\text{NMOS}),\qquad V_{D} < V_{B}\ (\text{PMOS}) - The condition every source and drain junction must satisfy, at every instant.
Body effect: V_T = V_{T0}+\gamma\left(\sqrt{2\phi_F+V_{SB}}-\sqrt{2\phi_F}\right) - The price of a source that is not at the body potential - the reason stacked devices are weaker.
Well capacitance: C_{well} = \frac{\varepsilon_s}{W_{dep}} - The n-well to substrate junction is a large reverse-biased diode, and its capacitance loads the supply.
Latch-up condition: \beta_{npn}\,\beta_{pnp} > 1 - The parasitic thyristor latches when the loop gain of the two bipolars exceeds unity.

Consider a PMOS whose n-well is accidentally left floating rather than tied to the supply. Its source sits at 1.8 V and the well drifts down through junction leakage. Once the well falls about 0.6 V below the source, the source-to-well junction forward biases and injects holes into the well. Those holes are collected by the substrate, which is exactly the current that turns on the parasitic thyristor. The circuit works on the bench for minutes and then fails catastrophically on a supply transient.

Why is an n-well tied to the supply rather than simply left unconnected, given that no current is meant to flow into it?

Because the source and drain junctions inside it must stay reverse biased at every instant, and a floating well has no defined potential - leakage and capacitive coupling will move it. Once the well drifts far enough below a p-type source, that junction forward biases and injects current into the substrate, which is the trigger condition for latch-up. Tying it to the supply through a low-resistance tap fixes the potential and gives injected current somewhere harmless to go.

3. Taps, guard rings, and the triple well

A body tap is a small heavily doped contact of the same type as the body it sits in - p+ into the p-substrate, n+ into the n-well - which connects that body to a rail through metal. Heavily doped, because the point is a low-resistance ohmic contact rather than a junction: a p+ region in p-type material does not form a diode, it forms a connection. In a standard cell library these taps are built into the cell rows, so a designer using standard cells gets them automatically and often never sees them. In custom or analogue layout they are placed by hand, and forgetting them is a classic and expensive mistake.

A guard ring is the same idea used defensively. A continuous ring of tap diffusion placed around a sensitive or a noisy block collects carriers injected into the substrate before they can reach anything else, and holds the local body potential firmly at its rail. Rings are used both ways round: around an aggressor such as an output driver, to stop it from injecting into the substrate, and around a victim such as an analogue reference, to stop substrate noise from reaching it. This is why mixed-signal layouts look so different from digital ones despite using the same devices.

The triple well takes the idea further. A deep n-type implant placed beneath a p-well isolates that p-well from the main substrate entirely, so a group of NMOS devices can sit in a body that is not at the global ground. Two things follow. Substrate noise from the rest of the chip can no longer reach those devices through their bodies, which is why the technique is standard for sensitive analogue and for on-chip oscillators. And the isolated body can be biased deliberately - forward biasing it lowers the threshold for speed, reverse biasing it raises the threshold to cut leakage in standby, which is the basis of body-bias power management.

First-order relation

V_{local} = I_{inj}\,R_{sub},\qquad R_{sub} \propto d

Derivation: Quantify how much reverse body bias is needed to cut leakage by a target factor.

Subthreshold current is exponential in threshold voltage with subthreshold swing S per decade.
The body-effect expression with a constant gamma describes the threshold shift.
The isolated well can be biased without forward biasing any junction.

I_{leak} \propto 10^{-V_T/S} - Subthreshold conduction falls by one decade for every S volts of threshold increase, by the definition of swing.
\frac{I_1}{I_0} = 10^{-\Delta V_T/S} - Take the ratio of two leakage currents differing only by a threshold shift.
\Delta V_T = S\,\log_{10}\!\left(\frac{I_0}{I_1}\right) - Rearrange for the threshold shift needed to achieve a target leakage reduction.
\Delta V_T = \gamma\left(\sqrt{2\phi_F+V_{SB}}-\sqrt{2\phi_F}\right) - The body effect supplies that shift, and this is what it costs in source-to-body bias.
V_{SB} = \left(\frac{\Delta V_T}{\gamma}+\sqrt{2\phi_F}\right)^{2}-2\phi_F - Solve for the required bias. The square makes it expensive: the shift is sublinear in V_SB.

A decade of leakage reduction costs one subthreshold swing of threshold shift, and the body bias needed for it grows quadratically. That is why body bias buys one or two decades in practice and not more.

Tap contact: p^{+}\ \text{in}\ p\text{-sub},\qquad n^{+}\ \text{in}\ n\text{-well} - Same type, heavily doped - an ohmic contact rather than a junction.
Local body rise: V_{local} = I_{inj} R_{sub} - What a tap is preventing. Keep it well under a junction turn-on.
Reverse body bias: V_{SB} > 0 \Rightarrow V_T \uparrow \Rightarrow I_{leak}\downarrow - Standby leakage reduction, available only with an isolated well.
Forward body bias: V_{SB} < 0 \Rightarrow V_T \downarrow \Rightarrow \text{speed}\uparrow - Buys speed at the cost of leakage and of junction margin. Limited to a few hundred millivolts.

Take a substrate sheet resistance of 10 ohms per square and an injected current of 1 mA reaching a tap 50 squares away. The local rise is 1e-3 x 500 = 0.5 V - just below a junction turn-on, so the design survives. Place the tap five times further away and the same event produces 2.5 V locally, which forward biases the junction hard and triggers the parasitic thyristor. Nothing about the transistors changed; only the distance to the nearest tap did.

A triple-well process lets a group of NMOS devices sit in a p-well isolated from the substrate. What does that buy, beyond noise isolation?

It makes the body a controllable terminal for that group. With the well isolated, its potential can be set independently of global ground, so the threshold voltage of those devices can be moved deliberately through the body effect - reverse biased in standby to raise the threshold and cut leakage, or forward biased when speed is needed. Without isolation the body is the whole substrate and cannot be biased per block.

4. Two transistors become an inverter, physically

Put an NMOS and a PMOS side by side, the NMOS in the substrate and the PMOS in an n-well. Connect their gates together with a single strip of polysilicon or metal running across both - that shared strip is the input. Connect their drains together in metal - that shared node is the output. Tie the NMOS source to ground and the PMOS source to the supply, and tie each body to the same rail as its own source. That is a CMOS inverter, and everything about its behaviour follows from that arrangement of six connections.

Two features of the layout matter as much as the schematic. The gate is one continuous strip crossing both diffusions, which is what makes the two devices genuinely share an input - and it is also why the input capacitance of an inverter is the sum of both gate capacitances rather than either one. And adjacent transistors in a chain share their diffusion regions: the drain of one and the source of the next are literally the same implanted island rather than two islands joined by wire. That sharing halves the junction capacitance at the shared node and is why layout style shows up directly in gate delay.

The complementary structure gives the property the whole logic family is named for. In either stable state exactly one of the two networks conducts, so there is no path from supply to ground and no static current beyond leakage. Current flows only while the input is transitioning, when both devices are momentarily on and the output capacitance is being charged or discharged. That is the reason CMOS displaced every earlier logic family: not that it is faster, but that a gate which is not switching costs almost nothing.

First-order relation

C_{L} = C_{db,n}+C_{db,p}+C_{wire}+C_{g,next}

Derivation: Show that the switching energy of a CMOS gate is independent of how fast or how resistively it switches.

The output node is a single capacitance C_L charged through a resistance from the supply.
The transition completes, so the node reaches the rail.
Leakage and short-circuit current are excluded, leaving the capacitive term alone.

E_{supply} = \int_0^{\infty} V_{DD}\,i(t)\,dt = V_{DD}\int_0^{\infty} i(t)\,dt - The supply is at a constant voltage, so its delivered energy is that voltage times the total charge that leaves it.
\int_0^{\infty} i(t)\,dt = C_L V_{DD} - All of that charge ends up on the load capacitance, which finishes the transition at the supply voltage.
E_{supply} = C_L V_{DD}^{2} - Substitute the previous line. Note that the resistance has already disappeared from the result.
E_{cap} = \tfrac{1}{2} C_L V_{DD}^{2} - Energy stored on a capacitor charged to the supply voltage.
E_{diss} = E_{supply}-E_{cap} = \tfrac{1}{2}C_L V_{DD}^{2} - The difference is dissipated in the pull-up resistance during the charging half.
E_{cycle} = \tfrac{1}{2}C_LV_{DD}^{2}+\tfrac{1}{2}C_LV_{DD}^{2} = C_LV_{DD}^{2} - On the discharge the stored half is dissipated in the pull-down. A full cycle costs the whole amount.

Exactly half the energy drawn from the supply is dissipated on every charging transition, whatever the resistance. A faster or wider transistor changes the delay and not the energy - only lowering C_L or V_DD changes the energy.

Input capacitance: C_{in} = C_{g,n}+C_{g,p} - One gate strip crossing both diffusions, so both gate capacitances load the driver.
Output load: C_L = C_{db,n}+C_{db,p}+C_{wire}+C_{g,next} - Self-load, wire, and the next stage. The complete inventory at the output node.
Propagation delay: t_p \approx 0.69\,R_{eq}C_L - The RC model, with R_eq an average of the resistance over the swing.
Switching energy: E = C_L V_{DD}^{2} - Per full cycle. Half is dissipated charging, half discharging, regardless of the resistance.
Dynamic power: P = \alpha C_L V_{DD}^{2} f - Activity factor times energy times frequency - the central number in CMOS power.

Take an inverter driving one identical copy, with C_db,n + C_db,p = 1.2 fF of self-load, 0.5 fF of wire and C_g,next = 2 fF. Then C_L = 3.7 fF. At V_DD = 1 V with R_eq = 8 kohm, t_p = 0.69 x 8e3 x 3.7e-15, about 20 ps. The switching energy is 3.7e-15 x 1, or 3.7 fJ per cycle, and at 1 GHz with an activity factor of 0.1 that gate burns 0.37 uW. Multiply by a hundred million gates and the reason power dominates modern design is arithmetic rather than opinion.

Why does an inverter draw essentially no current when its input is held steady at either rail, but a resistor-loaded inverter draws current in one of its two states?

Because the load is an active device that switches off rather than a fixed resistance. With the input at either rail, exactly one of the complementary networks conducts and the other is off, so there is no continuous path from supply to ground. A resistive load cannot switch off - whenever the pull-down device conducts, current flows through the resistor to ground for as long as that state is held.

CMOS Anatomy & Cross-Section

1. One transistor, from substrate to metal

Derivation: Show why a high-k dielectric lets the oxide get physically thicker without losing gate control.

The letters in MOSFET stand for metal-oxide-semiconductor. On a modern node, how many of those three materials are actually present as described?

2. The complementary pair: wells, and why the bodies go to opposite rails

Derivation: Show why body ties are placed repeatedly across a die rather than once per well.

Why is an n-well tied to the supply rather than simply left unconnected, given that no current is meant to flow into it?

3. Taps, guard rings, and the triple well

Derivation: Quantify how much reverse body bias is needed to cut leakage by a target factor.

A triple-well process lets a group of NMOS devices sit in a p-well isolated from the substrate. What does that buy, beyond noise isolation?

4. Two transistors become an inverter, physically

Derivation: Show that the switching energy of a CMOS gate is independent of how fast or how resistively it switches.

Why does an inverter draw essentially no current when its input is held steady at either rail, but a resistor-loaded inverter draws current in one of its two states?

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