Timing, Interconnect & Power

Chapter 9. Logical Effort and Path Optimization

9.1 Logical effort definitions

Logical effort compares a gate input capacitance with an inverter delivering the same output current. Electrical effort represents external load. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is D = sum(g_i h_i + p_i); path effort F = G B H. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

D = sum(g_i h_i + p_i); path effort F = G B H.

The design consequence is concrete: The method separates topology from sizing and gives a fast architecture-level estimate before detailed characterization. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. A path has total effort F = 256 and 4 stages. Estimate equal stage effort.

Solution. Work backward from the load. Parasitic delay, branching, discrete cells, slew, and wire load determine the implementable sizes.

f = F^(1/N) = 4.00

1. Which approximation in the relation for logical effort definitions is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

9.2 Optimal stage effort

For N stages with no branching, delay is minimized approximately when each stage bears equal effort. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is f_hat = F^(1/N); N_opt is near ln(F) when parasitics are modest. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

f_hat = F^(1/N); N_opt is near ln(F) when parasitics are modest.

The design consequence is concrete: The optimum is broad, so routing, available cells, slew limits, and power often justify a nearby nonmathematical choice. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. A path has total effort F = 1024 and 5 stages. Estimate equal stage effort.

Solution. Work backward from the load. Parasitic delay, branching, discrete cells, slew, and wire load determine the implementable sizes.

f = F^(1/N) = 4.00

1. Which approximation in the relation for optimal stage effort is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

9.3 Branching effort

A path that drives off-path loads pays branching effort in addition to the load that continues toward the destination. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is b = C_total/C_onpath; B = product(b_i). Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

b = C_total/C_onpath; B = product(b_i).

The design consequence is concrete: Buffer placement can isolate large side loads and prevent them from taxing the critical path. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. A path has total effort F = 64 and 3 stages. Estimate equal stage effort.

Solution. Work backward from the load. Parasitic delay, branching, discrete cells, slew, and wire load determine the implementable sizes.

f = F^(1/N) = 4.00

1. Which approximation in the relation for branching effort is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

9.4 Sizing a worked path

A path solution works backward from the load, assigning each stage input capacitance so stage effort approaches the chosen target. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is C_in,i = g_i C_out,i / f_i. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

C_in,i = g_i C_out,i / f_i.

The design consequence is concrete: Round to legal cells, recalculate effort, then check slew and physical congestion rather than treating continuous widths as implementable. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. A path has total effort F = 256 and 4 stages. Estimate equal stage effort.

Solution. Work backward from the load. Parasitic delay, branching, discrete cells, slew, and wire load determine the implementable sizes.

f = F^(1/N) = 4.00

1. Which approximation in the relation for sizing a worked path is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

9.5 Limits of the model

Logical effort assumes comparable waveform shapes and abstracts voltage-dependent resistance, Miller effects, stack state, and interconnect distribution. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is Use it for topology and initial sizing; use characterized STA and extracted simulation for signoff. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

Use it for topology and initial sizing; use characterized STA and extracted simulation for signoff.

The design consequence is concrete: A simple model is valuable when its error is understood and bounded. It becomes dangerous when precision formatting disguises omitted physics. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. A path has total effort F = 1024 and 5 stages. Estimate equal stage effort.

Solution. Work backward from the load. Parasitic delay, branching, discrete cells, slew, and wire load determine the implementable sizes.

f = F^(1/N) = 4.00

1. Which approximation in the relation for limits of the model is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

Chapter 10. Interconnect, Coupling, and Signal Integrity

10.1 Wire resistance and capacitance

Scaled transistors become faster while long global wires remain distributed RC networks with geometry-dependent resistance and capacitance. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is R = rho L/(wt); C includes ground and coupling components. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

R = rho L/(wt); C includes ground and coupling components.

The design consequence is concrete: Repeater insertion trades additional gate energy and area for a lower quadratic wire-delay penalty. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. A uniform wire has total R = 70 Ω and C = 120 fF. Estimate its open-ended distributed-RC 50% delay.

Solution. The 0.38RC estimate is a planning value. Coupling, driver resistance, receiver threshold, vias, and inductance belong in signoff.

t₅₀ ≈ 0.38RC = 3.19 ps

1. Which approximation in the relation for wire resistance and capacitance is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

10.2 Elmore delay

Elmore delay approximates a monotone RC tree by summing each capacitance weighted by resistance shared with the observation path. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is t_E = sum_k C_k R_common,k. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

t_E = sum_k C_k R_common,k.

The design consequence is concrete: It is fast, additive, and physically intuitive, making it useful for placement and buffering decisions. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. A uniform wire has total R = 100 Ω and C = 180 fF. Estimate its open-ended distributed-RC 50% delay.

Solution. The 0.38RC estimate is a planning value. Coupling, driver resistance, receiver threshold, vias, and inductance belong in signoff.

t₅₀ ≈ 0.38RC = 6.84 ps

1. Which approximation in the relation for elmore delay is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

10.3 Crosstalk and Miller effect

A victim wire sees effective capacitance that depends on aggressor direction and timing; opposite switching is slower than same-direction switching. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is C_eff may range roughly from C_g to C_g+2C_c for aligned ideal transitions. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

C_eff may range roughly from C_g to C_g+2C_c for aligned ideal transitions.

The design consequence is concrete: Coupling is both a delay problem and a functional noise problem. Temporal overlap matters as much as physical adjacency. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. A uniform wire has total R = 40 Ω and C = 80 fF. Estimate its open-ended distributed-RC 50% delay.

Solution. The 0.38RC estimate is a planning value. Coupling, driver resistance, receiver threshold, vias, and inductance belong in signoff.

t₅₀ ≈ 0.38RC = 1.22 ps

1. Which approximation in the relation for crosstalk and miller effect is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

10.4 Inductance, ringing, and termination

Fast edges make package and long-wire inductance relevant even when the clock frequency is modest. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is V_L = L di/dt; Z_0 = sqrt(L_prime/C_prime). Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

V_L = L di/dt; Z_0 = sqrt(L_prime/C_prime).

The design consequence is concrete: Edge rate, not toggle rate, determines whether a connection behaves as a transmission line. Source damping can trade rise time for cleaner settling. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. A uniform wire has total R = 70 Ω and C = 120 fF. Estimate its open-ended distributed-RC 50% delay.

Solution. The 0.38RC estimate is a planning value. Coupling, driver resistance, receiver threshold, vias, and inductance belong in signoff.

t₅₀ ≈ 0.38RC = 3.19 ps

1. Which approximation in the relation for inductance, ringing, and termination is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

10.5 Clock and reset distribution

Clock and reset networks combine insertion delay, skew, jitter, duty-cycle distortion, variation, and high switching power. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is T_available = T_clk - uncertainty - skew - setup. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

T_available = T_clk - uncertainty - skew - setup.

The design consequence is concrete: Balanced trees, meshes, useful skew, shielding, and local gating solve different parts of the distribution problem. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. A uniform wire has total R = 100 Ω and C = 180 fF. Estimate its open-ended distributed-RC 50% delay.

Solution. The 0.38RC estimate is a planning value. Coupling, driver resistance, receiver threshold, vias, and inductance belong in signoff.

t₅₀ ≈ 0.38RC = 6.84 ps

1. Which approximation in the relation for clock and reset distribution is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

Chapter 11. Power: Dynamic, Static, Short-Circuit, and Glitch

11.1 Dynamic switching energy

Charging a capacitance from an ideal supply draws C V^2 of energy; half is stored and half dissipated in the pull-up path. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is E_0to1 = C_L V_DD^2; P_dyn = alpha C_L V_DD^2 f. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

E_0to1 = C_L V_DD^2; P_dyn = alpha C_L V_DD^2 f.

The design consequence is concrete: Voltage has quadratic leverage, while activity and capacitance are linear levers. Clock networks have alpha near one and deserve special attention. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. A node has activity 0.15, C = 40 fF, VDD = 1.0 V, and f = 800 MHz. Estimate dynamic power.

Solution. This is only the node's capacitive switching term. Internal, short-circuit, glitch, clock, leakage, and regulator losses remain.

Pdyn = αCVDD²f = 4.800 µW

1. Which approximation in the relation for dynamic switching energy is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

11.2 Internal and short-circuit power

Cells consume energy in internal nodes and through simultaneous pull-up/pull-down conduction, beyond external load charging. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is P_cell = P_switching + P_internal + P_leakage. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

P_cell = P_switching + P_internal + P_leakage.

The design consequence is concrete: Library power tables depend on input slew, output load, state, and transition. Poor slew increases both delay and internal energy. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. A node has activity 0.25, C = 80 fF, VDD = 1.2 V, and f = 1200 MHz. Estimate dynamic power.

Solution. This is only the node's capacitive switching term. Internal, short-circuit, glitch, clock, leakage, and regulator losses remain.

Pdyn = αCVDD²f = 34.560 µW

1. Which approximation in the relation for internal and short-circuit power is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

11.3 Leakage power

Standby power sums state-dependent subthreshold, gate, and junction leakage and rises strongly with temperature. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is P_leak = V_DD I_leak. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

P_leak = V_DD I_leak.

The design consequence is concrete: Power gating, high-threshold cells, stack effect, reverse body bias, and state assignment attack different components and have wake-up costs. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. A node has activity 0.08, C = 20 fF, VDD = 0.8 V, and f = 500 MHz. Estimate dynamic power.

Solution. This is only the node's capacitive switching term. Internal, short-circuit, glitch, clock, leakage, and regulator losses remain.

Pdyn = αCVDD²f = 0.512 µW

1. Which approximation in the relation for leakage power is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

11.4 Glitch power

Reconvergent path imbalance can charge and discharge nodes without performing useful architectural work. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is E_glitch approximates number_of_partial_swings times C (Delta V)^2. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

E_glitch approximates number_of_partial_swings times C (Delta V)^2.

The design consequence is concrete: Pipelining, path balancing, operand isolation, and hazard-aware logic reduce glitch activity, sometimes more effectively than small capacitance savings. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. A node has activity 0.15, C = 40 fF, VDD = 1.0 V, and f = 800 MHz. Estimate dynamic power.

Solution. This is only the node's capacitive switching term. Internal, short-circuit, glitch, clock, leakage, and regulator losses remain.

Pdyn = αCVDD²f = 4.800 µW

1. Which approximation in the relation for glitch power is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

11.5 Energy-delay tradeoffs

Minimum energy and minimum delay occur at different voltages and sizes. Upsizing lowers resistance while raising capacitance and leakage. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is EDP = E t_d; ED^2P weights delay more strongly. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

EDP = E t_d; ED^2P weights delay more strongly.

The design consequence is concrete: Choose a metric tied to workload and latency constraints, then evaluate it across PVT and activity rather than one nominal point. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. A node has activity 0.25, C = 80 fF, VDD = 1.2 V, and f = 1200 MHz. Estimate dynamic power.

Solution. This is only the node's capacitive switching term. Internal, short-circuit, glitch, clock, leakage, and regulator losses remain.

Pdyn = αCVDD²f = 34.560 µW

1. Which approximation in the relation for energy-delay tradeoffs is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

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