Reliability, Layout & Signoff

Chapter 18. ESD, Latch-Up, and Back-Powering

18.1 ESD event models

Human-body, charged-device, and system-level events inject different current waveforms and stress paths. On-chip qualification is not the same as board immunity. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is Peak stress depends on source capacitance, series resistance, inductance, and clamp dynamic resistance. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

Peak stress depends on source capacitance, series resistance, inductance, and clamp dynamic resistance.

The design consequence is concrete: A robust path turns on quickly, keeps terminal voltage below damage limits, and carries current without local heating failure. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. A 2.5 V pin drives an unpowered 1.2 V rail through a 0.35 V clamp and 220 Ω path. Estimate injected current.

Solution. Clamp dynamic resistance, rail loading, current limits, and absolute-maximum injection ratings must also be checked.

Iinject ≈ (Vpin−Vrail−Vf)/R = 4.32 mA

1. Which approximation in the relation for esd event models is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

18.2 Clamp and rail network

Diodes, snapback devices, rail clamps, and distributed metal cooperate as a network; path resistance can dominate clamp voltage. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is V_pin = V_trigger/path + I_ESD(R_clamp+R_metal). Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

V_pin = V_trigger/path + I_ESD(R_clamp+R_metal).

The design consequence is concrete: A strong clamp placed far away can be ineffective at a vulnerable thin-oxide gate because interconnect raises local voltage. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. A 3.3 V pin drives an unpowered 1.8 V rail through a 0.35 V clamp and 470 Ω path. Estimate injected current.

Solution. Clamp dynamic resistance, rail loading, current limits, and absolute-maximum injection ratings must also be checked.

Iinject ≈ (Vpin−Vrail−Vf)/R = 2.45 mA

1. Which approximation in the relation for clamp and rail network is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

18.3 Latch-up physics

Parasitic lateral and vertical bipolar transistors form a silicon-controlled rectifier between supply rails. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is Latch condition requires loop gain beta_npn beta_pnp >= 1 with sufficient injection and well/substrate voltage drop. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

Latch condition requires loop gain beta_npn beta_pnp >= 1 with sufficient injection and well/substrate voltage drop.

The design consequence is concrete: Guard rings, frequent well taps, lower substrate resistance, spacing, and controlled injection reduce susceptibility. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. A 1.8 V pin drives an unpowered 1.0 V rail through a 0.35 V clamp and 100 Ω path. Estimate injected current.

Solution. Clamp dynamic resistance, rail loading, current limits, and absolute-maximum injection ratings must also be checked.

Iinject ≈ (Vpin−Vrail−Vf)/R = 4.50 mA

1. Which approximation in the relation for latch-up physics is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

18.4 Back-powering

A driven signal entering an unpowered domain can forward-bias an input clamp or parasitic path and raise the supposedly off rail. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is I_inject is set by external drive, series impedance, clamp behavior, and off-rail loads. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

I_inject is set by external drive, series impedance, clamp behavior, and off-rail loads.

The design consequence is concrete: Back-power can cause reliability stress, phantom operation, reset failure, or excessive standby current. Use fail-safe I/O or isolation. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. A 2.5 V pin drives an unpowered 1.2 V rail through a 0.35 V clamp and 220 Ω path. Estimate injected current.

Solution. Clamp dynamic resistance, rail loading, current limits, and absolute-maximum injection ratings must also be checked.

Iinject ≈ (Vpin−Vrail−Vf)/R = 4.32 mA

1. Which approximation in the relation for back-powering is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

18.5 Reliability-oriented debug

Electrical overstress often leaves subtle leakage or parametric drift before catastrophic failure. Localization combines current signatures, emission, thermal imaging, and physical analysis. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is Energy density and peak field, not only average power, determine damage. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

Energy density and peak field, not only average power, determine damage.

The design consequence is concrete: Preserve evidence: limit current, record the exact sequence, compare virgin controls, and avoid repeated stress after first failure. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. A 3.3 V pin drives an unpowered 1.8 V rail through a 0.35 V clamp and 470 Ω path. Estimate injected current.

Solution. Clamp dynamic resistance, rail loading, current limits, and absolute-maximum injection ratings must also be checked.

Iinject ≈ (Vpin−Vrail−Vf)/R = 2.45 mA

1. Which approximation in the relation for reliability-oriented debug is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

Chapter 19. Layout, Stick Diagrams, DRC, LVS, and PEX

19.1 Layout as electrical design

Physical layout determines parasitic resistance, capacitance, coupling, stress, matching, and current density while implementing the schematic connectivity. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is Geometry maps to R, C, device W/L, and reliability constraints. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

Geometry maps to R, C, device W/L, and reliability constraints.

The design consequence is concrete: A compact drawing is not automatically a fast or robust circuit; diffusion sharing and short wires must be balanced against coupling and access. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. PEX reports 32 Ω series resistance and 12 fF shunt capacitance on a local node. Estimate the RC time constant.

Solution. An extracted network can be distributed and coupled, so total R times total C is only a screening estimate.

τ = RC = 0.384 ps

1. Which approximation in the relation for layout as electrical design is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

19.2 Stick diagrams and Euler paths

Stick diagrams abstract topology and help order transistors so complementary networks share diffusion with few breaks. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is An Euler trail uses every network edge once; compatible PDN/PUN trails can align gates. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

An Euler trail uses every network edge once; compatible PDN/PUN trails can align gates.

The design consequence is concrete: The method reveals efficient series/parallel ordering before detailed design rules obscure topology. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. PEX reports 55 Ω series resistance and 20 fF shunt capacitance on a local node. Estimate the RC time constant.

Solution. An extracted network can be distributed and coupled, so total R times total C is only a screening estimate.

τ = RC = 1.100 ps

1. Which approximation in the relation for stick diagrams and euler paths is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

19.3 Design-rule checking

DRC encodes manufacturability constraints such as width, spacing, enclosure, density, antenna, and pattern restrictions. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is A DRC-clean layout satisfies the encoded rule deck, not every possible yield or reliability concern. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

A DRC-clean layout satisfies the encoded rule deck, not every possible yield or reliability concern.

The design consequence is concrete: Rule intent matters: minimum geometry may be legal but unwise for high current, matching, or analog sensitivity. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. PEX reports 18 Ω series resistance and 6 fF shunt capacitance on a local node. Estimate the RC time constant.

Solution. An extracted network can be distributed and coupled, so total R times total C is only a screening estimate.

τ = RC = 0.108 ps

1. Which approximation in the relation for design-rule checking is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

19.4 Layout-versus-schematic

LVS extracts devices and connectivity and compares them with the intended netlist, accounting for legal series/parallel equivalence. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is LVS success requires matched device type, dimensions, multiplicity, and net connectivity. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

LVS success requires matched device type, dimensions, multiplicity, and net connectivity.

The design consequence is concrete: A clean LVS is necessary but does not prove correct pin labels, power intent, parameter interpretation, or parasitic acceptability. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. PEX reports 32 Ω series resistance and 12 fF shunt capacitance on a local node. Estimate the RC time constant.

Solution. An extracted network can be distributed and coupled, so total R times total C is only a screening estimate.

τ = RC = 0.384 ps

1. Which approximation in the relation for layout-versus-schematic is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

19.5 Parasitic extraction

PEX converts layout geometry into distributed R and C, and sometimes inductance, for post-layout analysis. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is Post-layout delay and noise depend on coupling state and distributed topology, not only total capacitance. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

Post-layout delay and noise depend on coupling state and distributed topology, not only total capacitance.

The design consequence is concrete: Use extraction corners and coupling settings aligned with the signoff question. Reduce networks only with an error target. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. PEX reports 55 Ω series resistance and 20 fF shunt capacitance on a local node. Estimate the RC time constant.

Solution. An extracted network can be distributed and coupled, so total R times total C is only a screening estimate.

τ = RC = 1.100 ps

1. Which approximation in the relation for parasitic extraction is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

Chapter 20. PVT, Characterization, and Static Timing Analysis

20.1 Process, voltage, and temperature corners

PVT corners bound correlated device and environment shifts, while statistical analysis addresses local variation and tails. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is Delay generally rises with weaker process and lower voltage; temperature behavior can invert at low voltage. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

Delay generally rises with weaker process and lower voltage; temperature behavior can invert at low voltage.

The design consequence is concrete: Corner naming is shorthand for a model set, not a universal physical truth. Verify which devices and interconnect assumptions each corner contains. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. An STA endpoint has required arrival 1100 ps and actual arrival 1040 ps. Compute slack and interpret the sign.

Solution. Positive setup slack is margin; negative slack is a violation. Scenario validity still depends on constraints, exceptions, derates, and waveform range.

slack = required − actual = 60 ps

1. Which approximation in the relation for process, voltage, and temperature corners is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

20.2 Cell characterization

Libraries tabulate timing constraints, delay, transition, power, noise, and function over slew, load, state, and corners. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is An NLDM arc is commonly a two-dimensional lookup over input transition and output capacitance. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

An NLDM arc is commonly a two-dimensional lookup over input transition and output capacitance.

The design consequence is concrete: Interpolation is trustworthy only inside characterized ranges; extrapolation flags design or library coverage problems. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. An STA endpoint has required arrival 1350 ps and actual arrival 1420 ps. Compute slack and interpret the sign.

Solution. Positive setup slack is margin; negative slack is a violation. Scenario validity still depends on constraints, exceptions, derates, and waveform range.

slack = required − actual = -70 ps

1. Which approximation in the relation for cell characterization is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

20.3 Setup and hold STA

STA propagates arrival and required times through timing graphs without enumerating input vectors, using sensitization and constraint models. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is Slack = required arrival - actual arrival. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

Slack = required arrival - actual arrival.

The design consequence is concrete: False paths and multicycle paths are functional assertions, not optimization hints. Incorrect exceptions can hide silicon failures. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. An STA endpoint has required arrival 850 ps and actual arrival 790 ps. Compute slack and interpret the sign.

Solution. Positive setup slack is margin; negative slack is a violation. Scenario validity still depends on constraints, exceptions, derates, and waveform range.

slack = required − actual = 60 ps

1. Which approximation in the relation for setup and hold sta is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

20.4 On-chip variation and derates

Variation changes launch and capture paths differently. AOCV/POCV methods model depth, distance, and statistical correlation more realistically than fixed derates. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is Common-path pessimism removal credits shared clock segments whose variation is correlated. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

Common-path pessimism removal credits shared clock segments whose variation is correlated.

The design consequence is concrete: More pessimism is not automatically safer if it drives harmful fixes or masks model inconsistency; the goal is calibrated margin. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. An STA endpoint has required arrival 1100 ps and actual arrival 1040 ps. Compute slack and interpret the sign.

Solution. Positive setup slack is margin; negative slack is a violation. Scenario validity still depends on constraints, exceptions, derates, and waveform range.

slack = required − actual = 60 ps

1. Which approximation in the relation for on-chip variation and derates is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

20.5 Timing closure workflow

Closure coordinates logic restructuring, sizing, buffering, placement, routing, clock design, power integrity, and constraints. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is Every fix changes capacitance, slew, congestion, power, and often another corner. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

Every fix changes capacitance, slew, congestion, power, and often another corner.

The design consequence is concrete: Prioritize root causes and path groups, preserve hold guardband, and validate after extraction. Late brute-force upsizing can create a power-grid spiral. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. An STA endpoint has required arrival 1350 ps and actual arrival 1420 ps. Compute slack and interpret the sign.

Solution. Positive setup slack is margin; negative slack is a violation. Scenario validity still depends on constraints, exceptions, derates, and waveform range.

slack = required − actual = -70 ps

1. Which approximation in the relation for timing closure workflow is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

More in CMOS & VLSI

• Silicon PhysicsSemiconductor foundations, junctions, MOS electrostatics, NMOS/PMOS operation, compact models, and scaled-device nonidealities.
• Timing & PowerRC delay, logical effort, interconnect, crosstalk, dynamic and short-circuit power, leakage, and glitches.
• Gates & Pass LogicStatic and complex gates, transmission gates, degraded levels, hazards, sizing, and an interactive transistor-level gate atlas.
• Inverter DesignThe voltage-transfer curve, switching threshold, noise margins, sizing, capacitance, delay, and transition behavior.
• Sequential & CDCLatches, flip-flops, setup and hold, clocking, metastability, synchronizers, handshakes, and multi-bit crossings.
• Memory Circuits6T SRAM operation and margins, array periphery, DRAM sensing and refresh, and Flash storage mechanisms.
• I/O & PDNI/O pads, level shifting, open-drain buses, simultaneous switching, ground bounce, decoupling, and PDN behavior.
• BenchcraftMeasurement loading, bandwidth, grounding, current and thermal observation, fault isolation, and evidence capture.
• Scaling FrontierDennard scaling, leakage and power walls, variability, FinFET quantization, and gate-all-around devices.
• Course MapThe complete learning map: ten focused areas, 22 chapters, 110 lessons, worked examples, exercises, references, and progress tracking.
• CMOS & VLSIA curated silicon curriculum from energy bands and the MOS capacitor through gates, timing, power, memory, I/O, reliability, layout, signoff, FinFETs and GAAFETs—with 110 lessons, worked calculations, bench notes, progress tracking, and transistor-level labs.