The CMOS Inverter

Chapter 5. CMOS Inverter: Static Behavior

5.1 Complementary pull-up and pull-down

The CMOS inverter pairs a PMOS pull-up with an NMOS pull-down so one network ideally disconnects in each stable logic state. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is V_OH ~= V_DD and V_OL ~= 0 when static leakage is small. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

V_OH ~= V_DD and V_OL ~= 0 when static leakage is small.

The design consequence is concrete: Complementarity produces rail-to-rail restoration and near-zero ideal static current, the architectural reason CMOS displaced ratioed logic. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. For matched square-law strengths at VDD = 1.0 V, VTN = 0.25 V, and |VTP| = 0.28 V, estimate the inverter switching point.

Solution. Equate the saturation currents, then verify the device regions. Characterized currents and the full VTC are still required for signoff.

VM ≈ (VDD + VTN − |VTP|) / 2 = 0.485 V

1. Which approximation in the relation for complementary pull-up and pull-down is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

5.2 Voltage-transfer characteristic

The VTC follows operating-region changes as input rises: NMOS turn-on, both-device competition, then PMOS turn-off. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is At the switching point V_M, I_DN(V_M,V_M)=|I_DP(V_M,V_M-V_DD)|. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

At the switching point V_M, I_DN(V_M,V_M)=|I_DP(V_M,V_M-V_DD)|.

The design consequence is concrete: The steep middle region supplies gain and logic restoration. Device strength ratio positions the transition relative to the rails. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. For matched square-law strengths at VDD = 1.2 V, VTN = 0.25 V, and |VTP| = 0.28 V, estimate the inverter switching point.

Solution. Equate the saturation currents, then verify the device regions. Characterized currents and the full VTC are still required for signoff.

VM ≈ (VDD + VTN − |VTP|) / 2 = 0.585 V

1. Which approximation in the relation for voltage-transfer characteristic is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

5.3 Noise margins

Noise margins compare guaranteed output levels with the input thresholds defined where VTC slope equals -1. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is NM_L = V_IL-V_OL; NM_H = V_OH-V_IH. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

NM_L = V_IL-V_OL; NM_H = V_OH-V_IH.

The design consequence is concrete: A centered switching point is helpful but not sufficient; actual margins depend on VTC slope and output rails across PVT. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. For matched square-law strengths at VDD = 0.8 V, VTN = 0.25 V, and |VTP| = 0.28 V, estimate the inverter switching point.

Solution. Equate the saturation currents, then verify the device regions. Characterized currents and the full VTC are still required for signoff.

VM ≈ (VDD + VTN − |VTP|) / 2 = 0.385 V

1. Which approximation in the relation for noise margins is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

5.4 Sizing and beta ratio

Because hole mobility is lower, a PMOS is commonly wider than an NMOS to balance transition currents, though modern libraries tune using characterized delay. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is beta_n/beta_p = (mu_n C_ox W_n/L_n)/(mu_p C_ox W_p/L_p). Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

beta_n/beta_p = (mu_n C_ox W_n/L_n)/(mu_p C_ox W_p/L_p).

The design consequence is concrete: Balanced rise/fall delay, centered VTC, input capacitance, leakage, and layout pitch are competing objectives rather than one sizing problem. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. For matched square-law strengths at VDD = 1.0 V, VTN = 0.25 V, and |VTP| = 0.28 V, estimate the inverter switching point.

Solution. Equate the saturation currents, then verify the device regions. Characterized currents and the full VTC are still required for signoff.

VM ≈ (VDD + VTN − |VTP|) / 2 = 0.485 V

1. Which approximation in the relation for sizing and beta ratio is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

5.5 Worked VTC and contention example

A useful hand calculation partitions the input axis, assumes device regions, equates currents, and then checks whether the assumed regions were self-consistent. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is For matched square-law devices, V_M ~= (V_DD+V_TN-|V_TP|)/2. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

For matched square-law devices, V_M ~= (V_DD+V_TN-|V_TP|)/2.

The design consequence is concrete: The equation shows how thresholds and strength ratio move the switching point, while simulation supplies modern-model accuracy. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. For matched square-law strengths at VDD = 1.2 V, VTN = 0.25 V, and |VTP| = 0.28 V, estimate the inverter switching point.

Solution. Equate the saturation currents, then verify the device regions. Characterized currents and the full VTC are still required for signoff.

VM ≈ (VDD + VTN − |VTP|) / 2 = 0.585 V

1. Which approximation in the relation for worked vtc and contention example is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

Chapter 6. Inverter Dynamics, Delay, and Loading

6.1 Capacitance inventory

Output load includes gate capacitance, diffusion junctions, overlap, wiring, coupling, and measurement fixtures. Internal capacitance is voltage dependent. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is C_L = sum(C_gate + C_diff + C_wire + C_coupling + C_probe). Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

C_L = sum(C_gate + C_diff + C_wire + C_coupling + C_probe).

The design consequence is concrete: A credible delay model begins with an ownership map of every capacitance and the node that charges it. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. An effective conducting path of 2.5 kΩ drives 24 fF. Estimate the 50% transition delay.

Solution. Use a lumped RC estimate, then account for voltage-dependent resistance, input slew, charge sharing, and distributed capacitance in transient verification.

t₅₀ ≈ 0.69RC = 41.4 ps

1. Which approximation in the relation for capacitance inventory is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

6.2 First-order propagation delay

A switching transistor can be approximated by an effective resistance charging or discharging a lumped capacitance. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is t_pHL ~= 0.69 R_n,eq C_L; t_pLH ~= 0.69 R_p,eq C_L. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

t_pHL ~= 0.69 R_n,eq C_L; t_pLH ~= 0.69 R_p,eq C_L.

The design consequence is concrete: The 0.69 factor comes from a 50% crossing of a first-order exponential, so it changes with threshold convention and waveform shape. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. An effective conducting path of 4.0 kΩ drives 40 fF. Estimate the 50% transition delay.

Solution. Use a lumped RC estimate, then account for voltage-dependent resistance, input slew, charge sharing, and distributed capacitance in transient verification.

t₅₀ ≈ 0.69RC = 110.4 ps

1. Which approximation in the relation for first-order propagation delay is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

6.3 Slew dependence and short-circuit window

A slow input keeps both devices partially on, increases short-circuit current, and changes the effective drive during output transition. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is E_sc grows with input transition time and roughly with (V_DD-2V_T)^3 in simple models. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

E_sc grows with input transition time and roughly with (V_DD-2V_T)^3 in simple models.

The design consequence is concrete: Timing arcs must be characterized over both input slew and output load; a single intrinsic delay number is incomplete. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. An effective conducting path of 1.5 kΩ drives 16 fF. Estimate the 50% transition delay.

Solution. Use a lumped RC estimate, then account for voltage-dependent resistance, input slew, charge sharing, and distributed capacitance in transient verification.

t₅₀ ≈ 0.69RC = 16.6 ps

1. Which approximation in the relation for slew dependence and short-circuit window is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

6.4 Fan-out and effort

Electrical effort measures load relative to input capacitance; parasitic delay accounts for capacitance internal to the gate. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is d = g h + p; h = C_out/C_in. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

d = g h + p; h = C_out/C_in.

The design consequence is concrete: Stage effort distributes a large load across a chain. Equal effort is a robust starting point, then discrete cells and wiring refine it. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. An effective conducting path of 2.5 kΩ drives 24 fF. Estimate the 50% transition delay.

Solution. Use a lumped RC estimate, then account for voltage-dependent resistance, input slew, charge sharing, and distributed capacitance in transient verification.

t₅₀ ≈ 0.69RC = 41.4 ps

1. Which approximation in the relation for fan-out and effort is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

6.5 Ring oscillator extraction

An odd-numbered inverter loop oscillates because inversion and finite propagation delay prevent a static consistent state. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is t_pd,avg ~= 1/(2 N f_osc). Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

t_pd,avg ~= 1/(2 N f_osc).

The design consequence is concrete: A ring oscillator averages rising and falling delay under repeated switching and includes local wiring and loading. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. An effective conducting path of 4.0 kΩ drives 40 fF. Estimate the 50% transition delay.

Solution. Use a lumped RC estimate, then account for voltage-dependent resistance, input slew, charge sharing, and distributed capacitance in transient verification.

t₅₀ ≈ 0.69RC = 110.4 ps

1. Which approximation in the relation for ring oscillator extraction is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

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