Silicon Foundations & MOS Physics

Chapter 1. Semiconductor Foundations

1.1 Crystal, bonds, and energy bands

A silicon crystal is a periodic covalent lattice; the allowed electronic states collect into valence and conduction bands separated by an energy gap. Bands are what is left of atomic energy levels after 10^23 atoms per cubic centimetre are brought close enough to share electrons. Each discrete level splits into a near-continuum, and the gap between the highest filled band and the lowest empty one is what makes silicon useful: wide enough that thermal energy leaves most electrons bound, narrow enough that doping, light or a field can move a controllable number of them. A metal has no gap and cannot be switched off; an insulator's gap is too wide to switch on.

The first-order relation is E_g(Si, 300 K) ~= 1.12 eV; electron energy and electrostatic potential have opposite sign. On a band diagram the vertical axis is electron energy, so it runs opposite to electrostatic potential - a region at higher potential sits lower on the diagram. Band bending is therefore the same information as a potential profile, and the conduction-band slope dE_c/dx equals q times the electric field in a uniform material; the electron force is the negative of that energy gradient. Read a diagram by asking three questions in order: where are the bands flat (no field), which way do they bend (which way carriers roll), and where does the Fermi level sit relative to the band edges (how many carriers are there).

E_g(Si, 300 K) ~= 1.12 eV; electron energy and electrostatic potential have opposite sign.

Band diagrams are bookkeeping devices: slope encodes electric field, bending encodes spatial potential, and the Fermi level encodes occupancy. Silicon's approximately 1.12 eV room-temperature gap strongly influences intrinsic carrier concentration together with the band densities of states. Junction forward voltage depends on current density, temperature and device structure, not a universal 0.7 V value. Leakage often rises steeply with temperature, but no fixed doubling interval describes every mechanism and bias condition. When a design brief says a part must hold state at 125 degrees, the gap is the reason that is hard.

Worked example

Problem. Silicon's gap is 1.12 eV. Estimate how many more carriers are thermally excited across it at 400 K than at 300 K.

Solution. Pair generation follows exp(-E_g / 2kT). At 300 K, kT = 25.9 meV, so the exponent is -1120/(2 x 25.9) = -21.6. At 400 K, kT = 34.5 meV and the exponent is -1120/(2 x 34.5) = -16.2. The ratio is exp(21.6 - 16.2) = exp(5.4).

About 220x more intrinsic carriers at 400 K. The gap is what sets silicon's temperature ceiling.

1. Which approximation in the relation for crystal, bonds, and energy bands is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

1.2 Carriers and statistics

Electrons in the conduction band and holes in the valence band are mobile carriers. Nondegenerate silicon usually follows Boltzmann statistics. Doping does not create carriers so much as unbalance them. Adding donors raises n, and the mass-action law np = n_i^2 forces p down by the same factor, so a region with 10^17 donors has about 10^3 holes per cubic centimetre - ten orders of magnitude apart. That asymmetry is the whole reason a junction rectifies, and it is why minority-carrier effects can be invisible in a DC measurement and dominant in a transient.

The first-order relation is n = n_i exp((E_F-E_i)/kT), p = n_i exp((E_i-E_F)/kT), and np = n_i^2 at equilibrium. n_i at 300 K is roughly 10^10 per cubic centimetre, and doping levels of interest run from 10^15 to 10^20. Work in exponents rather than decimals and the arithmetic stays trivial. Charge neutrality gives n - p = N_D - N_A, which combined with np = n_i^2 solves the general case; for N_D much larger than n_i simply take n = N_D. Two assumptions hide in that shortcut: complete ionisation, and Boltzmann statistics rather than Fermi-Dirac.

n = n_i exp((E_F-E_i)/kT), p = n_i exp((E_i-E_F)/kT), and np = n_i^2 at equilibrium.

Doping moves the Fermi level and changes majority-carrier density, but charge neutrality and ionization must still be satisfied. At heavy source/drain doping, nondegenerate statistics can fail and band-gap narrowing and concentration-dependent mobility become important. Incomplete ionization is especially important at low temperature; it is not a universal consequence of crossing one heavy-doping value at room temperature. That is why source/drain sheet resistance and contact resistance do not scale the way a textbook extrapolation predicts.

Worked example

Problem. A sample is doped with N_D = 1e17 and N_A = 9e16 cm^-3. Find n and p at 300 K with n_i = 1e10 cm^-3.

Solution. Charge neutrality uses the net doping: 1e17 - 9e16 = 1e16 cm^-3, still far above n_i, so n = 1e16. Then p = n_i^2/n = 1e20/1e16 = 1e4 cm^-3.

n = 1e16, p = 1e4 cm^-3. Compensation cut the electron count tenfold and raised the hole count tenfold - taking the donor concentration alone would have been wrong by an order of magnitude.

1. Which approximation in the relation for carriers and statistics is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

1.3 Drift, diffusion, and mobility

An electric field causes drift while a concentration gradient causes diffusion; both mechanisms contribute to current. Drift and diffusion are the same random thermal motion seen under two different conditions. Carriers always move fast and randomly, around 10^7 cm/s thermal velocity, scattering every picosecond or so. A field biases that walk slightly in one direction, which is drift; a concentration gradient means more carriers wander out of the dense region than into it, which is diffusion. Mobility measures how much net velocity a field buys before the next scattering event destroys it.

The first-order relation is J_n = q n mu_n E + q D_n grad(n); D_n/mu_n = kT/q. The Einstein relation D/mu = kT/q is the strongest unit check available in device physics, and at 300 K kT/q is 25.9 mV - a number worth memorising, because it appears in the diode equation, in subthreshold slope, and in every thermal-voltage expression on this course. This simple Einstein relation assumes nondegenerate carriers in the usual thermal transport model; outside that regime, use the appropriate generalized relation rather than treating every deviation as an algebra error.

J_n = q n mu_n E + q D_n grad(n); D_n/mu_n = kT/q.

The Einstein relation connects transport to thermal energy and provides a powerful unit and sign check. Mobility is not a material constant, which is the mistake that most often invalidates a hand calculation. It falls with doping through impurity scattering, with temperature through phonon scattering, and with vertical gate field through surface roughness scattering at the oxide interface. The last one matters most here: inversion-layer mobility in a real MOSFET is roughly half the bulk value, and it degrades further as oxides thin and vertical fields rise.

Worked example

Problem. Electrons have mu_n = 1400 cm^2/(V.s) at 300 K. Find the diffusion coefficient, and the drift velocity in a field of 1 kV/cm.

Solution. Einstein gives D = mu x kT/q = 1400 x 0.0259 = 36.3 cm^2/s. Drift velocity is mu x E = 1400 x 1000 = 1.4e6 cm/s. Check it against the saturation velocity of about 1e7 cm/s before trusting the linear relation.

D = 36.3 cm^2/s and v = 1.4e6 cm/s - already about 14 percent of the saturation velocity, so the low-field assumption is closer to failing than it looks.

1. Which approximation in the relation for drift, diffusion, and mobility is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

1.4 Generation, recombination, and lifetime

Carrier populations return toward equilibrium through radiative, Auger, and trap-assisted processes; silicon logic is often dominated by Shockley-Read-Hall paths. Generation and recombination are the mechanisms that push a disturbed carrier population back toward np = n_i^2. In silicon, an indirect-gap material, direct band-to-band recombination is improbable because it needs a phonon to conserve momentum, so the dominant path is trap-assisted: a defect state near mid-gap captures an electron, then a hole, and the pair is gone. This is why silicon makes poor LEDs and excellent switches, and why deep-level contamination is the defect class fabs care about most.

The first-order relation is R_SRH = (np-n_i^2)/(tau_p(n+n_1)+tau_n(p+p_1)). The SRH expression peaks for traps at mid-gap and for regions where n and p are comparable - which is precisely the depletion region, not the neutral bulk. When estimating junction leakage, apply generation to the depleted volume and diffusion to the neutral regions, and expect the depletion term to dominate at room temperature in a reverse-biased silicon junction.

R_SRH = (np-n_i^2)/(tau_p(n+n_1)+tau_n(p+p_1)).

Lifetime controls leakage transients, junction recovery, and photogenerated charge collection, even when a DC logic model hides it. Lifetime is invisible in a static logic model and decisive in a dynamic one. A floating node - a DRAM cell, a dynamic logic node, a sample-and-hold capacitor - holds its value only for as long as generation takes to refill the depletion region beneath it. Retention time, refresh interval, and the maximum clock period of a dynamic gate are all the same physical number wearing different names.

Worked example

Problem. A depletion region 0.3 um wide has a generation lifetime of 1 ms, with n_i = 1e10 cm^-3. Estimate the generation current density.

Solution. J_gen = q n_i W / (2 tau) = 1.602e-19 x 1e10 x 3e-5 / (2 x 1e-3). The numerator is 4.81e-14, so J = 2.4e-11 A/cm^2. Note it scales with n_i, which roughly doubles every 8 degrees.

About 24 pA/cm^2. Small per unit area, and the dominant reverse-leakage mechanism in a silicon junction at room temperature.

1. Which approximation in the relation for generation, recombination, and lifetime is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

1.5 Poisson equation and electrostatics

Device electrostatics couples charge density to potential and must be solved with material boundaries and terminal constraints. Almost every result in the next three chapters is Poisson's equation solved under a different set of approximations. Charge sets the curvature of potential, the first integral gives field, the second gives potential itself. The depletion approximation - assume the charge is exactly the ionised dopant density inside some boundary and exactly zero outside - is what turns an intractable coupled problem into two integrations, and it is accurate enough because the transition region is only a few Debye lengths wide.

The first-order relation is d^2 psi/dx^2 = -rho/epsilon; E = -d psi/dx. Work the same sequence every time: state the charge density in each region, integrate once for field and apply continuity of displacement at each interface, integrate again for potential and apply the terminal or built-in boundary conditions. Displacement, not field, is continuous across a dielectric boundary, so field jumps by the permittivity ratio - roughly a factor of three at the silicon-oxide interface, which is exactly why oxide field is much higher than silicon field.

d^2 psi/dx^2 = -rho/epsilon; E = -d psi/dx.

Most MOS derivations are controlled approximations to Poisson equation: identify the charge region, integrate once for field and again for potential. The boundary conditions carry more of the physics than the differential equation does. A correct integration with the wrong contact potential produces a clean-looking answer that is simply wrong, and that failure mode is common because the algebra offers no warning. Check limits instead: as doping rises the depletion width should shrink, and as the oxide thins the same gate voltage should produce more inversion charge.

Worked example

Problem. A one-sided abrupt junction has N_D = 1e16 cm^-3 under 5 V of reverse bias. Find the depletion width and the peak field.

Solution. W = sqrt(2 x 1.04e-12 x 5 / (1.602e-19 x 1e16)) = sqrt(6.49e-9) = 8.06e-5 cm. The peak field sits at the junction: E = qN_D W / eps = 1.602e-19 x 1e16 x 8.06e-5 / 1.04e-12.

W = 0.81 um with a peak field of 124 kV/cm - comfortably below the roughly 300 kV/cm breakdown field at this doping.

1. Which approximation in the relation for poisson equation and electrostatics is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

Chapter 2. Junctions and the MOS Capacitor

2.1 PN junction equilibrium

Carrier diffusion across a newly formed junction leaves fixed ionized dopants and creates a depletion field that opposes further diffusion. Bringing n- and p-type silicon into contact starts a diffusion current that immediately defeats itself. Electrons leaving the n side expose fixed positive donors; holes leaving the p side expose fixed negative acceptors. The resulting dipole builds a field that opposes further diffusion, and equilibrium is reached when drift exactly cancels diffusion at every point - not when the current is large, but when two large opposing currents balance to zero net flow.

The first-order relation is V_bi = V_T ln(N_A N_D/n_i^2); W = sqrt(2 epsilon_s (V_bi-V_a)/q (1/N_A+1/N_D)). V_bi is a logarithm of a doping product, so it is remarkably insensitive: two decades of doping change moves it by about 120 mV. Expect roughly 0.7 to 0.9 V for typical silicon junctions and treat a computed value far outside that as an arithmetic error. Depletion width, by contrast, follows a square root of the lighter doping and does move substantially.

V_bi = V_T ln(N_A N_D/n_i^2); W = sqrt(2 epsilon_s (V_bi-V_a)/q (1/N_A+1/N_D)).

Depletion grows mainly into the more lightly doped side, so junction geometry and well doping shape both capacitance and breakdown. Depletion spreads almost entirely into the lightly doped side, because charge must balance across the junction and it takes far more volume to find the same number of dopants. That single fact explains the layout of every drift region, the doping of every well, and why a source/drain-to-well junction depletes into the well rather than into the diffusion.

Worked example

Problem. Find V_bi for a silicon junction with N_A = 1e17 and N_D = 1e16 cm^-3 at 300 K, then find how much it changes if both dopings are raised tenfold.

Solution. V_bi = 0.0259 x ln(1e17 x 1e16 / 1e20) = 0.0259 x ln(1e13) = 0.0259 x 29.9. Raising both tenfold multiplies the argument by 100, adding ln(100) = 4.6 to the logarithm.

0.775 V, rising only to 0.894 V for a hundredfold increase in the doping product. V_bi is a logarithm, so it barely moves.

1. Which approximation in the relation for pn junction equilibrium is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

2.2 Junction capacitance and breakdown

Reverse bias changes depletion width and therefore junction capacitance; high fields eventually trigger avalanche or tunneling. A reverse-biased junction is a capacitor whose plate separation grows with voltage, which makes it nonlinear in a way that matters. Junction capacitance falls as roughly V^-1/2 for an abrupt profile and V^-1/3 for a graded one. Breakdown then arrives by one of two mechanisms with opposite temperature behaviour: avalanche multiplication, where carriers gain enough energy between collisions to ionise the lattice, and Zener tunnelling, where the bands bend so steeply that electrons tunnel straight across.

The first-order relation is C_j = C_j0/(1+V_R/Phi_0)^m; E_max scales approximately with sqrt(N V_R). The two mechanisms separate by voltage and are told apart by temperature coefficient rather than by the shape of the knee. Below roughly 5 V the mechanism is tunnelling and breakdown voltage falls with temperature; above roughly 6 V it is avalanche and breakdown voltage rises with temperature, because hotter lattices scatter carriers before they reach ionising energy. Between the two the coefficients cancel, which is what a temperature-compensated reference diode exploits.

C_j = C_j0/(1+V_R/Phi_0)^m; E_max scales approximately with sqrt(N V_R).

Sidewall capacitance can dominate a compact diffusion, while corner fields often set real breakdown below a one-dimensional estimate. In digital CMOS these junctions are parasitic, not designed, and their capacitance is charged and discharged on every transition. Diffusion capacitance is a real fraction of the load on a small gate, it is voltage dependent so it is not a single number, and it is the reason shared-diffusion layout styles are worth the effort. Avalanche then reappears as a reliability limit in I/O and ESD structures.

Worked example

Problem. A junction has C_j0 = 1 fF/um^2, phi_0 = 0.8 V and grading m = 0.5. Find its capacitance at 0 V and at 3 V reverse bias.

Solution. C_j = C_j0 / (1 + V_R/phi_0)^m. At 0 V the bracket is 1, so C_j = C_j0 = 1 fF/um^2. At 3 V the bracket is (1 + 3/0.8) = 4.75, and with m = 0.5 that is a square root: 2.18. So C_j = 1/2.18 = 0.46 fF/um^2.

1.0 fF/um^2 falling to 0.46 fF/um^2 - a factor of 2.2 across the swing, which is why any single linearised value has to state the range it was linearised over.

1. Which approximation in the relation for junction capacitance and breakdown is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

2.3 MOS structure and flat band

The MOS capacitor stacks metal or polysilicon, oxide, and semiconductor; work-function difference and fixed oxide charge shift the voltage needed for flat bands. The MOS capacitor is the MOSFET with the current path ignored, and understanding it is understanding the transistor. Gate, oxide and semiconductor form a capacitor whose lower plate is not a metal but a semiconductor that can supply several different kinds of charge, and which of them it supplies is what the gate voltage selects. Flat band is the reference condition: the bias at which no bands bend and no charge is induced.

The first-order relation is V_FB = Phi_MS - Q_ox/C_ox; C_ox = epsilon_ox/t_ox. Flat band is not zero volts. The work-function difference between gate and substrate offsets it, and any fixed charge in the oxide offsets it further by Q_f/C_ox. Both terms are process constants rather than design variables, and both are folded into threshold voltage later, which is why V_T has a component you cannot compute from geometry alone.

V_FB = Phi_MS - Q_ox/C_ox; C_ox = epsilon_ox/t_ox.

Flat-band voltage is not automatically zero. It carries process information and becomes part of the threshold-voltage budget. The oxide is the smallest and most stressed dimension in the whole device. At a few nanometres it is tens of atomic layers thick and holds several megavolts per centimetre in normal operation. Everything gained by thinning it - more inversion charge per volt, more drive, better electrostatic control - is paid for in gate tunnelling current and time-dependent dielectric breakdown, which is the trade that eventually forced high-k dielectrics.

Worked example

Problem. A gate stack has t_ox = 3 nm with k = 3.9, and carries fixed oxide charge of 5e10 elementary charges per cm^2. Find C_ox and the flat-band shift.

Solution. C_ox = 3.9 x 8.854e-14 / 3e-7 = 1.15e-6 F/cm^2. The charge density is 5e10 x 1.602e-19 = 8.01e-9 C/cm^2, and the shift is -Q_f/C_ox.

C_ox = 1.15 uF/cm^2; the fixed charge shifts flat band by -7.0 mV, and that goes directly into the threshold voltage.

1. Which approximation in the relation for mos structure and flat band is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

2.4 Accumulation, depletion, inversion

Gate bias redistributes surface charge: majority carriers accumulate, a depletion region forms, and eventually minority carriers create inversion. Three regimes, selected by gate bias. Negative gate on p-type substrate attracts holes to the surface: accumulation, a majority-carrier response that is fast and behaves like a plain capacitor. Positive gate pushes holes away and exposes fixed acceptors: depletion, where a growing depletion capacitance appears in series with the oxide and total capacitance falls. Push further and the surface becomes electron-rich: inversion, where the surface behaves as n-type despite the substrate being p-type.

The first-order relation is |Q_B| = sqrt(2 q epsilon_s N_A psi_s); strong inversion is commonly referenced at psi_s = 2 phi_F. Strong inversion is conventionally defined at surface potential equal to 2*phi_F, the point at which surface electron density equals bulk hole density. The definition is a convention, not a physical discontinuity - inversion charge grows exponentially through the transition rather than switching on - and that softness is exactly what subthreshold conduction is. Treating 2*phi_F as a hard edge is what makes hand-calculated threshold values disagree with measured ones.

|Q_B| = sqrt(2 q epsilon_s N_A psi_s); strong inversion is commonly referenced at psi_s = 2 phi_F.

The surface potential does not track gate voltage one-for-one because oxide and depletion capacitances divide the applied voltage. Whether a high-frequency C-V measurement shows the inversion branch depends on where minority carriers can come from. In a two-terminal capacitor they must be generated thermally, which is slow, so the curve stays at the depletion minimum. In a real MOSFET the source and drain supply them instantly, which is why the transistor inverts at any usable frequency while the isolated capacitor does not.

Worked example

Problem. For N_A = 1e17 cm^-3, find the surface potential at strong inversion and the depletion width there.

Solution. phi_F = 0.0259 x ln(1e17/1e10) = 0.0259 x 16.1 = 0.417 V, so strong inversion is at 2 phi_F = 0.835 V. Then W_dep = sqrt(2 x 1.04e-12 x 0.835 / (1.602e-19 x 1e17)) = sqrt(1.084e-10).

psi_s = 0.835 V at a depletion width of 104 nm. Past this point inversion charge screens the gate and the depletion region stops growing.

1. Which approximation in the relation for accumulation, depletion, inversion is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

2.5 Threshold voltage and body effect

Threshold is a model boundary marking strong inversion, not a microscopic switch. Source-to-body bias changes the depletion charge and shifts threshold. Threshold voltage is a bookkeeping sum, not a single mechanism: the flat-band offset, plus the band bending needed to reach strong inversion, plus the gate charge required to support the depletion charge underneath. Body effect follows directly. Reverse-biasing the source relative to the substrate widens the depletion region, which means more depletion charge, which means the gate must supply more before inversion begins - so V_T rises.

The first-order relation is V_T = V_FB + 2 phi_F + gamma sqrt(2 phi_F+V_SB); gamma = sqrt(2q epsilon_s N_A)/C_ox. Gamma, the body-effect coefficient, is proportional to the square root of substrate doping and inversely proportional to C_ox, so it rises with doping and with oxide thickness. Use the square-root expression rather than a linear approximation: the effect is strongly sublinear, and a linear fit calibrated at low V_SB overestimates badly at high V_SB.

V_T = V_FB + 2 phi_F + gamma sqrt(2 phi_F+V_SB); gamma = sqrt(2q epsilon_s N_A)/C_ox.

Keep the body terminal explicit during hand analysis. Stacked devices and pass transistors frequently have nonzero V_SB. Body effect is why stacked transistors are not simply series resistors. The upper device in a NAND stack sits with its source above the substrate potential, so its threshold is raised and its drive is reduced, and the penalty grows with stack depth. This is the physical origin of the sizing rules for tall stacks, and the reason a four-input NAND is worse than the transistor count alone suggests.

Worked example

Problem. With N_A = 1e17 cm^-3 and t_ox = 3 nm, compute the body factor and the threshold shift from 0 to 1 V of source-body bias.

Solution. gamma = sqrt(2 x 1.602e-19 x 1.04e-12 x 1e17) / 1.15e-6 = 1.825e-7 / 1.15e-6 = 0.159. The shift is 0.159 x (sqrt(1.835) - sqrt(0.835)) = 0.159 x (1.355 - 0.914).

gamma = 0.16 V^0.5, so 1 V of body bias costs 70 mV of threshold - and a four-high stack pays a version of that cumulatively.

1. Which approximation in the relation for threshold voltage and body effect is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

Chapter 3. Long-Channel MOSFET Operation

3.1 Channel formation and charge sheet

A MOSFET conducts when gate bias creates an inversion sheet linking source and drain. The gradual-channel approximation treats lateral variation as slow. Above threshold the inversion layer is a sheet of mobile electrons perhaps a nanometre thick, held against the oxide by the vertical field and free to move along the channel. The charge-sheet approximation treats it as a surface charge density with no thickness, so the channel becomes a one-dimensional resistor whose local conductivity the gate sets pointwise. Every long-channel current expression is that picture plus an integration along the channel.

The first-order relation is Q_i(x) ~= -C_ox[V_GS-V_T-V(x)]. Local inversion charge is C_ox times the local gate overdrive, and the overdrive falls along the channel because the channel potential rises from source to drain. Integrating that varying charge from source to drain is where the V_DS^2/2 term comes from - it is not a correction bolted on, it is the consequence of the channel not being uniform.

Q_i(x) ~= -C_ox[V_GS-V_T-V(x)].

Think in charge, not merely in resistance: current is carrier velocity multiplied by the inversion charge available at each channel position. The approximation is a gradual-channel one: it assumes the vertical field dominates the lateral field, so each slice can be solved as a one-dimensional MOS capacitor. That holds when the channel is long compared with the depletion depths. Every short-channel effect in chapter 4 is a way this assumption fails, which is why they arrive together rather than one at a time.

Worked example

Problem. With C_ox = 1.15 uF/cm^2 and an overdrive of 0.6 V, find the inversion charge density and the electron sheet density at the source end.

Solution. |Q_inv| = C_ox x V_ov = 1.15e-6 x 0.6 = 6.9e-7 C/cm^2. Dividing by the elementary charge converts it to a carrier count: 6.9e-7 / 1.602e-19.

0.69 uC/cm^2, or 4.3e12 electrons per square centimetre. A sheet density, because the inversion layer has no useful thickness.

1. Which approximation in the relation for channel formation and charge sheet is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

3.2 Linear-region current

At small drain bias the inversion sheet exists along the full channel and the device behaves as a voltage-controlled resistor. For small V_DS the channel is nearly uniform and the device is a voltage-controlled resistor: current rises linearly with V_DS and the slope is set by gate overdrive. This is the regime a pass transistor or an analogue switch operates in, and the regime a logic gate spends the end of its transition in, when the output has nearly settled and the driving device is barely dropping any voltage.

The first-order relation is I_D = mu C_ox (W/L)[(V_GS-V_T)V_DS - V_DS^2/2]. Keep the V_DS^2/2 term unless V_DS is genuinely small compared with the overdrive; dropping it is a triode approximation, not the triode equation, and it overestimates current by a growing margin as V_DS rises. On-resistance is the derivative at the origin, roughly 1/(mu C_ox (W/L) V_ov), which is the number a switch design actually needs.

I_D = mu C_ox (W/L)[(V_GS-V_T)V_DS - V_DS^2/2].

The quadratic term is the signature of channel charge tapering toward the drain; dropping it is safe only for very small V_DS. On-resistance depends on overdrive, so a pass transistor's resistance changes as its own source voltage moves - which is what makes a bare NMOS pass gate slow down as it approaches its threshold-degraded high level, and why the transmission gate that fixes this is worth two transistors.

Worked example

Problem. A device with k' = 200 uA/V^2 and W/L = 10 has V_ov = 0.6 V. Find I_D at V_DS = 0.1 V, and the error from dropping the V_DS squared term.

Solution. I_D = 200e-6 x 10 x (0.6 x 0.1 - 0.01/2) = 2e-3 x (0.06 - 0.005) = 110 uA. Without the squared term it would be 2e-3 x 0.06 = 120 uA.

110 uA. The simplification overestimates by 9 percent even at a V_DS one sixth of the overdrive.

1. Which approximation in the relation for linear-region current is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

3.3 Saturation and square law

Saturation begins when the local overdrive at the drain reaches zero in the long-channel charge-sheet model. As V_DS rises the drain-end overdrive falls, and at V_DS equal to the overdrive the inversion charge at the drain reaches zero: pinch-off. Current does not stop, because the carriers arriving at the pinch-off point are swept across the short high-field region by drift. Beyond that, further drain voltage lands on the pinched region rather than the channel, so the current the channel delivers stops changing - saturation.

The first-order relation is I_Dsat = 0.5 mu C_ox (W/L)(V_GS-V_T)^2 for V_DS >= V_GS-V_T. The square-law expression is a long-channel result and should be treated as such. It is close enough for hand analysis and design intuition, it is what logical effort and most first-cut sizing assume, and it is quantitatively wrong for any modern short-channel device, where drive is closer to linear in overdrive. Use it to reason, not to predict silicon.

I_Dsat = 0.5 mu C_ox (W/L)(V_GS-V_T)^2 for V_DS >= V_GS-V_T.

Pinch-off does not mean current stops. Carriers traverse a high-field drain region after channel charge vanishes locally. Saturation is what makes a MOSFET an amplifier and a well-behaved logic device: output current set mostly by input voltage and only weakly by output voltage. It is also why gate delay depends on overdrive squared in the long-channel picture, and why supply-voltage scaling hurts speed superlinearly until velocity saturation flattens the relationship.

Worked example

Problem. The same device is taken to V_DS = 1.2 V. Find where saturation begins and the saturation current.

Solution. Saturation begins where the drain-end overdrive reaches zero, at V_DS = V_ov = 0.6 V. Substituting that into the triode expression gives I_D = (200e-6/2) x 10 x 0.6^2 = 1e-3 x 0.36 = 360 uA, and the long-channel model holds it there for any larger V_DS.

V_DS,sat = 0.6 V and I_D,sat = 360 uA, flat thereafter - until channel-length modulation is added, which is the next lesson.

1. Which approximation in the relation for saturation and square law is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

3.4 Transconductance and output resistance

Small-signal parameters linearize terminal response around a bias point and connect device physics to gain and delay. Transconductance is how much drain current a change of gate voltage buys, and output resistance is how much drain current leaks away with drain voltage. Their product is the intrinsic gain, the most a single device can deliver. In digital terms g_m is drive strength and r_o is the flatness of the saturation region that keeps a logic level from drooping.

The first-order relation is g_m = dI_D/dV_GS ~= 2I_D/V_OV; r_o ~= 1/(lambda I_D). Three forms of g_m are equivalent in the long-channel model: 2I_D/V_ov, mu C_ox (W/L) V_ov, and the square root form sqrt(2 mu C_ox (W/L) I_D). Which one to use is decided by what is being held fixed. At fixed current, widening a device raises g_m only as a square root, which is the single most useful efficiency fact in analogue sizing and the reason brute-force widening stops paying.

g_m = dI_D/dV_GS ~= 2I_D/V_OV; r_o ~= 1/(lambda I_D).

The ratio g_m/I_D is a useful inversion-level metric, while intrinsic gain g_m r_o exposes the cost of short channels. g_m/I_D is the figure of merit worth carrying, because it states how much transconductance each unit of current is buying, and it is bounded above by the subthreshold limit. A device biased at low overdrive is efficient and slow; one at high overdrive is fast and wasteful. Digital design lives at the wasteful end deliberately, because it is buying delay rather than gain.

Worked example

Problem. For that device in saturation, compute g_m by all three routes and confirm they agree.

Solution. From overdrive: 200e-6 x 10 x 0.6 = 1.2 mS. From current: 2 x 360e-6 / 0.6 = 1.2 mS. From the square-root form: sqrt(2 x 200e-6 x 10 x 360e-6) = sqrt(1.44e-6) = 1.2 mS.

1.2 mS by every route. One quantity, three algebraic forms, each answering a different design question.

1. Which approximation in the relation for transconductance and output resistance is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

3.5 PMOS symmetry and sign discipline

A PMOS uses holes and opposite terminal polarities, but its magnitude equations mirror the NMOS when voltages are defined consistently. The PMOS is the same physics with every sign reversed: n-well substrate, p+ source and drain, holes as carriers, negative threshold, current flowing from source to drain with the source at the higher potential. Nothing new happens; the bookkeeping is simply easier to get wrong, and a sign error in a PMOS expression produces a result that looks plausible and is backwards.

The first-order relation is V_SG > |V_TP| turns on a PMOS; saturation when V_SD >= V_SG-|V_TP|. Pick one convention and hold it: either work with magnitudes throughout and reason about direction separately, or carry signed quantities consistently and never mix the two in one expression. Most errors come from a half-converted derivation. The source of a PMOS is its higher-potential terminal, which in a pull-up network is the supply rail - not the node you drew at the bottom of the schematic.

V_SG > |V_TP| turns on a PMOS; saturation when V_SD >= V_SG-|V_TP|.

Use source-referenced positive magnitudes for quick design, then convert once to simulator sign conventions. Hole mobility is roughly two to three times lower than electron mobility, so a PMOS must be correspondingly wider for equal drive. That ratio sets the beta ratio of every static gate, drives the area cost of pull-up networks, and is the reason NAND is generally preferred over NOR in static CMOS: NAND puts the series stack in the faster NMOS network and the parallel devices in the slower PMOS one.

Worked example

Problem. A PMOS must match that NMOS for drive with mu_n/mu_p = 2.5. Find its W/L and the resulting input capacitance of the pair.

Solution. Equal drive needs (W/L)_p = 2.5 x (W/L)_n = 25. Gate capacitance scales with gate area, so the pair presents 1 + 2.5 = 3.5 times what the NMOS alone would.

W/L = 25 for the PMOS, and 3.5x the NMOS gate capacitance for the pair - the real price of a symmetric transfer characteristic.

1. Which approximation in the relation for pmos symmetry and sign discipline is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

Chapter 4. MOSFET Nonidealities and Compact Models

4.1 Channel-length modulation

The drain depletion region shortens the effective channel after pinch-off, so saturation current rises with drain voltage. Saturation current is not quite flat because the pinch-off point moves. As V_DS rises the pinched region widens, the effective channel length shortens, and current rises in proportion. The effect is fractional - a fixed absolute shortening matters more in a short device - which is why lambda scales roughly as 1/L and why analogue designers reach for long devices when they need output resistance.

The first-order relation is I_D ~= I_Dsat(1+lambda V_DS); r_o = 1/(lambda I_D). The (1 + lambda V_DS) factor is an empirical patch, not a derivation, and lambda is extracted by fitting rather than computed from geometry. It is adequate for hand analysis of gain and completely inadequate for predicting a real device's output conductance, which is set by several mechanisms at once. Do not extrapolate a fitted lambda outside the bias range it was fitted in.

I_D ~= I_Dsat(1+lambda V_DS); r_o = 1/(lambda I_D).

CLM reduces analog gain and changes logic transition current, particularly at low supply where devices operate near the boundary. In digital design channel-length modulation shows up as a logic level that is not quite rail-to-rail under load and as a current that keeps creeping up with drain voltage. In analogue design it is the dominant limit on single-stage gain. Same mechanism, two entirely different consequences, which is why the two disciplines size devices so differently.

Worked example

Problem. A device delivers 360 uA at V_DS = 0.6 V and 396 uA at 1.6 V. Extract lambda, r_o and the intrinsic gain.

Solution. The ratio is 1.1, so (1 + 1.6L)/(1 + 0.6L) = 1.1. Expanding: 1 + 1.6L = 1.1 + 0.66L, so 0.94L = 0.1. Then r_o = 1/(lambda I_D) and A_v = g_m r_o with g_m = 1.2 mS.

lambda = 0.106 V^-1, r_o = 26 kohm, intrinsic gain 31. Note the gain is a device ceiling, independent of how much current you bias it at.

1. Which approximation in the relation for channel-length modulation is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

4.2 Subthreshold conduction

Below threshold, diffusion of weak-inversion carriers produces an exponential current rather than an ideal off state. Below threshold the channel does not switch off; it becomes exponential. With the surface weakly inverted, current is carried by diffusion rather than drift, and it falls by a fixed factor for each fixed decrement of gate voltage. The controlling ratio is a capacitive divider between the oxide and the depletion capacitance beneath it, which decides how much of a gate-voltage change actually reaches the surface potential.

The first-order relation is I_D proportional to exp((V_GS-V_T)/(n V_T))(1-exp(-V_DS/V_T)); S = n ln(10) V_T. Subthreshold swing has a hard floor of (kT/q) ln 10, about 60 mV per decade at room temperature, and real devices land at 70 to 90 because the body factor n exceeds one. That floor is thermodynamic, not technological: no amount of process work removes it while conduction is over a thermal barrier. It also scales with absolute temperature, so a hot part leaks more for two compounding reasons.

I_D proportional to exp((V_GS-V_T)/(n V_T))(1-exp(-V_DS/V_T)); S = n ln(10) V_T.

The thermal limit near room temperature is about 60 mV/decade for an ideal MOS electrostatic gate; real slope is larger. This single number decides how far supply voltage can fall. Threshold must stay high enough that a device off at zero volts leaks acceptably, and supply must stay well above threshold for speed - and the 60 mV floor is what stops threshold from scaling with supply. It is the reason Dennard scaling ended, and the reason subthreshold-slope-beating devices are an active research target.

Worked example

Problem. A device has C_dep/C_ox = 0.45. Find its subthreshold swing at 27 C and 110 C, and the gate swing needed for six decades of turn-off at each.

Solution. n = 1.45. At 300 K, S = 1.45 x 25.9 x 2.303 = 86 mV/dec, so six decades cost 519 mV. At 383 K, kT/q = 33.0 mV so S = 1.45 x 33.0 x 2.303 = 110 mV/dec, and six decades cost 661 mV.

86 mV/dec becoming 110 mV/dec - 142 mV more gate swing for the same turn-off, before the threshold shift is even counted.

1. Which approximation in the relation for subthreshold conduction is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

4.3 DIBL, velocity saturation, and mobility loss

Short channels allow drain potential and high fields to influence the source barrier and carrier velocity. Three separate short-channel mechanisms, often conflated. DIBL is electrostatic: the drain's depletion region reaches far enough that drain voltage helps invert the channel, lowering threshold. Velocity saturation is transport: above roughly 10^4 V/cm carriers stop accelerating and cap out near 10^7 cm/s, so current becomes linear in overdrive rather than quadratic. Mobility degradation is scattering: high vertical field presses carriers against a rough interface.

The first-order relation is V_T(V_DS) ~= V_T0-eta V_DS; I_on tends toward W C_ox V_OV v_sat rather than a square law. Tell them apart by what each depends on. DIBL is a threshold shift proportional to V_DS and shows as a vertical offset between I-V curves taken at different drain voltages. Velocity saturation changes the exponent of the overdrive dependence, visible as drive current growing linearly rather than quadratically. Mobility degradation shows as transconductance falling at high gate voltage. Fitting one with another's model produces parameters that do not extrapolate.

V_T(V_DS) ~= V_T0-eta V_DS; I_on tends toward W C_ox V_OV v_sat rather than a square law.

Current becomes closer to linear in overdrive, degrading classical sizing intuition while making source-end electrostatics central. Velocity saturation is why increasing supply voltage stopped buying proportional speed, and why gate delay became much less sensitive to overdrive than square-law reasoning predicts. DIBL is why leakage rises with supply as well as with temperature. Both are reasons that hand calculations based on chapter 3 give the right shape and the wrong number on a modern node.

Worked example

Problem. A short device has E_sat = 4e4 V/cm and L = 50 nm. Find the V_DS at which velocity saturation sets in, and compare it with an overdrive of 0.6 V.

Solution. The lateral field reaches E_sat when V_DS = E_sat x L = 4e4 x 50e-7 = 0.2 V. Long-channel pinch-off would not have occurred until V_DS reached the overdrive, 0.6 V.

0.2 V - the device is velocity limited at a third of the voltage where the square law expects saturation, so its drive is linear in overdrive rather than quadratic.

1. Which approximation in the relation for dibl, velocity saturation, and mobility loss is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

4.4 Leakage mechanisms

Standby current combines subthreshold, junction generation, gate tunneling, gate-induced drain leakage, and punchthrough. Off-state current is a sum of independent paths, not one number. Subthreshold conduction flows source to drain through the weakly inverted channel. Gate tunnelling flows straight through a thin oxide. Reverse-biased junctions leak by generation in their depletion regions. GIDL flows where a strong gate-to-drain field bends bands enough for band-to-band tunnelling in the overlap region. Each has a different bias and temperature dependence.

The first-order relation is I_leak,total is a sum of mechanisms with different voltage and temperature signatures. Identify which path dominates before trying to reduce anything, because the remedies conflict. Subthreshold leakage falls with higher threshold and lower temperature; gate leakage is nearly temperature independent and falls only with thicker or higher-k dielectric; GIDL gets worse when the gate is driven below the source, which is exactly what some low-power schemes do deliberately. A measurement at one temperature cannot separate them; a measurement at two can.

I_leak,total is a sum of mechanisms with different voltage and temperature signatures.

Optimization requires identifying the dominant path, because lowering one component can worsen another through geometry or threshold choices. Standby power in a large chip is this sum multiplied by hundreds of millions of devices, which is why leakage moved from a curiosity to a first-order design constraint. It is also why multi-threshold libraries exist: use low-threshold cells only on paths that need the speed, and pay standby current only where timing demands it.

Worked example

Problem. A block of 10 million gates leaks 5 nA each at 25 C on a 1 V supply. Find the standby power at 25 C and at 85 C.

Solution. At 25 C: 1e7 x 5e-9 x 1 = 50 mW. Leakage roughly doubles per ten degrees, so 60 degrees is a factor of 2^6 = 64, giving 320 nA per gate.

50 mW becoming 3.2 W for doing nothing at all. This is why leakage went from a curiosity to a first-order design constraint.

1. Which approximation in the relation for leakage mechanisms is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

4.5 Process variation and mismatch

Global process shifts move many devices together; local random variation creates pairwise mismatch. Both interact with voltage and temperature. Two devices drawn identically are not identical. Random dopant fluctuation is the largest term in small devices: the channel depletion region contains a countable number of dopant atoms, and Poisson statistics on a countable number is a percentage effect. Line-edge roughness, oxide thickness variation and metal-gate grain orientation add to it. The result is a threshold voltage that is a distribution, not a value.

The first-order relation is sigma(V_T) ~= A_VT/sqrt(WL); sigma(beta)/beta ~= A_beta/sqrt(WL). Pelgrom's law states that mismatch standard deviation scales as 1/sqrt(WL), so area buys matching - and it buys it slowly, since halving sigma costs four times the area. Separate systematic variation, which is correlated across a die and can be cancelled by layout technique or common-centroid arrangement, from random mismatch, which cannot be cancelled and can only be averaged down.

sigma(V_T) ~= A_VT/sqrt(WL); sigma(beta)/beta ~= A_beta/sqrt(WL).

Larger area improves matching but adds capacitance and routing parasitics. Common-centroid layout addresses gradients, not random noise. This is why the smallest devices on a chip are in SRAM cells and why SRAM is the first block to fail at a new node: a six-transistor cell relies on a fight between minimum-size devices, and a fight between two distributions has a failure tail. With millions of cells, a six-sigma tail is a real number of broken bits, which is why cell design is a yield problem rather than a circuit problem.

Worked example

Problem. An SRAM device is W = 60 nm, L = 30 nm in a process with A_VT = 3 mV.um. Find sigma(V_T), and compare with an analogue device ten times larger in each dimension.

Solution. Area is 0.06 x 0.03 = 1.8e-3 um^2, whose square root is 0.0424 um. So sigma = 3 / 0.0424 = 71 mV. The larger device has 100x the area, so sigma falls by the square root of 100.

71 mV for the SRAM device against 7.1 mV for the analogue one. Multiplied by millions of cells, that 71 mV tail is a yield number rather than a curiosity.

1. Which approximation in the relation for process variation and mismatch is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

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