Memory Circuits

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More in CMOS & VLSI

• Silicon PhysicsSemiconductor foundations, pn junctions, MOS electrostatics, NMOS/PMOS operation, compact models, and scaled-device nonidealities.
• Layout & SignoffESD, latch-up, back-powering, stick diagrams, layout, DRC/LVS/PEX, PVT, characterization, constraints, and STA.
• Timing & PowerRC delay, slew, logical effort, wire models, coupling, repeaters, dynamic and short-circuit power, leakage, and glitches.
• MOSFET DerivationsWhere the formulae come from: the gradual-channel integration, threshold and body effect, small-signal parameters, and the subthreshold floor.
• Dynamic CMOS & DominoPrecharge and evaluate, domino cascading, charge sharing and keepers - the fast logic family, and the honest account of why it faded.
• The Real Four-Terminal MOSFETThe device you actually get: four terminals, body diodes, five gate capacitances that move with operating region, series resistance and temperature.
• CMOS Anatomy & Cross-SectionWhat the silicon actually looks like: wells, diffusions, STI, the gate stack, contacts and taps - and why an inverter needs all of it.
• The FET FamilyEvery field-effect device on one map: junction, Schottky, insulated and heterojunction gates, and the geometry answers - FinFET, GAAFET and power devices.
• Inverter DesignVTC regions, switching threshold, noise margins, ratioing, sizing, load capacitance, transition behavior, and measurement.
• Gates & Pass LogicPull-up/pull-down duality, NAND/NOR/AOI/OAI sizing, transmission gates, degraded levels, hazards, and transistor-level inspection.
• Sequential & CDCLatches, flip-flops, setup/hold, clocking, metastability, synchronizers, handshakes, pulse and multi-bit crossings.
• I/O & PDNPads, level shifters, open-drain buses, simultaneous switching, ground bounce, decoupling, impedance, and PDN debug.