CMOS & VLSI

The FET Family

Every field-effect device on one map: junction, Schottky, insulated and heterojunction gates, and the geometry answers - FinFET, GAAFET and power devices.

Reviewed 2026-08-223,442 words

1. One charge-control law, four ways to build the gate

Every field-effect transistor does the same thing: a gate electrode sets an electrostatic condition that changes how much mobile charge sits in a channel, and a separate source-to-drain circuit moves that charge. The gate supplies displacement current while the voltage is changing and, ideally, no steady current at all. That separation is what makes a FET a nearly power-free control element, and it is the reason the family exists as a family - the members differ in how the gate couples to the channel, not in what the gate is for.

There are four ways to build that coupling, and naming them is more useful than memorising four sets of curves. A reverse-biased pn junction gives a JFET. A Schottky metal-semiconductor contact gives a MESFET. An insulating layer gives the MOSFET, which is why the older literature calls it an IGFET. A heterojunction between two materials of different bandgap gives a HEMT. Each choice fixes the gate capacitance per unit area, the permitted gate polarity and the gate leakage, and those three numbers largely determine what the device is good for.

The channel differs too, and it is a separate axis from the gate. A JFET modulates a doped channel that is already there. An enhancement MOSFET creates an inversion layer that does not exist at zero bias. A HEMT uses a two-dimensional electron gas formed at a material boundary. This is why enhancement and depletion are not synonyms for MOSFET and JFET: those words describe whether a channel exists at zero gate-to-source bias, and that is a design choice in several of these families. A part chosen for a fail-safe power-up state has to be checked against that behaviour, not against the letters FET.

First-order relation

I_D \approx \mu \frac{W}{L} C_g (V_{GS}-V_{TH}) V_{DS}

Derivation: Show that one charge-control expression covers every family, so the differences reduce to two parameters.

Drift transport in a low lateral field, so velocity is proportional to field.
The channel is thin enough to be described by a sheet charge density rather than a volume density.
V_DS is small enough that the channel charge is nearly uniform from source to drain.

Q_{ch} = C_g\,(V_{GS}-V_{TH}) - Charge control: the gate capacitance converts the voltage above threshold into mobile channel charge per unit area.
G_{ch} = \frac{W}{L}\,\mu\,Q_{ch} - Conductance of a sheet of charge - mobility turns charge into conductivity, and W over L is the geometry.
I_D = G_{ch}\,V_{DS} - Ohm's law for the channel, valid while the channel is nearly uniform.
I_D = \mu\,\frac{W}{L}\,C_g\,(V_{GS}-V_{TH})\,V_{DS} - Substitute the first two lines into the third.

The family differences collapse into C_g and V_TH. A MOSFET, a JFET, a MESFET and a HEMT all obey this expression at small V_DS; what changes is how the gate capacitance is built and what sets the threshold.

Charge control: Q_{ch} = C_g\,(V_{GS}-V_{TH}) - Mobile channel charge per unit area. Every family obeys this; they differ in what sets C_g and V_TH.
Insulated gate: C_{ox} = \frac{\varepsilon_{ox}}{t_{ox}} - MOSFET. A parallel-plate capacitor, so a thinner oxide buys more charge per volt.
Junction gate: C_j = \frac{\varepsilon_s}{W_{dep}} - JFET and MESFET. Voltage dependent, because the depletion width moves with bias.
Sheet conductance: G_{ch} = \frac{W}{L}\,q\,n_s\,\mu - n_s is the sheet carrier density, the natural unit for a channel with no useful thickness.

Take an insulated gate with t_ox = 2 nm and relative permittivity 3.9. Then C_ox = 3.9 x 8.854e-14 F/cm divided by 2e-7 cm, about 1.73 uF/cm^2. With 0.5 V of overdrive that is 0.86 uC/cm^2 of channel charge, roughly 5.4e12 electrons per square centimetre. A junction gate over a 100 nm depletion width gives about 1.04 nF/cm^2 - three orders of magnitude less charge per volt, which is why insulated gates won for dense logic.

Two devices are both called FETs and both have a gate. Why can one of them be destroyed by a forward gate bias that the other tolerates?

Because the gate coupling differs. A junction or Schottky gate is a diode: forward bias makes it conduct, so it stops being a near-zero-current control input and can be destroyed by the resulting current. An insulated gate has no conducting path at any polarity, and fails instead by dielectric breakdown once the field across the oxide gets too large.

2. JFET and MESFET: the gate is a reverse-biased diode

A JFET starts with a channel that already conducts. A doped bar runs from source to drain, and a gate region of the opposite type sits against it. Reverse-biasing the gate widens the junction depletion region, which eats into the conducting cross-section from the sides and squeezes the channel. Increase the reverse bias enough and the depletion regions meet in the middle: the channel is pinched off and the current saturates. Because the channel conducts at zero gate bias, the ordinary JFET is a depletion-mode device - normally on.

A MESFET replaces the pn junction with a metal-semiconductor Schottky contact. The physics of channel control is the same, a bias-dependent depletion region narrowing a doped channel, but the Schottky gate can be made much smaller and faster, and it works in materials such as gallium arsenide where a good insulating native oxide is not available. That combination made the GaAs MESFET the workhorse of microwave electronics for years, and it explains why the device is common in RF and rare in dense digital logic.

The word pinch-off causes more confusion here than anywhere else in device physics, because it names two different things. In a JFET, pinch-off is the gate voltage at which the depletion regions meet and the channel is cut off entirely - genuinely off. In a MOSFET, pinch-off names the drain-end condition at which inversion charge reaches zero and the device enters saturation, and current continues to flow. One word, two mechanisms, opposite implications for whether current is flowing. Reading a JFET datasheet with the MOSFET meaning in mind produces a device that is on when the design expected it off.

First-order relation

I_D = I_{DSS}\left(1-\frac{V_{GS}}{V_P}\right)^{2}

Derivation: Derive the Shockley square-law relation for a JFET from the depletion width that controls the channel.

Abrupt junction and the depletion approximation, so the depleted region has a sharp edge and contains only ionised dopants.
Uniform channel doping N_D, with a symmetric gate on both sides of a channel of half-thickness a.
Gradual channel approximation: the depletion width at any point is set by the local voltage.
Constant mobility and drift transport only.

W(y) = \sqrt{\frac{2\varepsilon_s\,(V_{bi}-V_{GS}+V(y))}{q N_D}} - Depletion width of a one-sided abrupt junction under the local reverse bias at position y along the channel.
b(y) = a - W(y) - The conducting half-thickness left over is the physical half-thickness minus what the depletion region has taken.
I_D = 2 q N_D \mu\,W_{ch}\,b(y)\,\frac{dV}{dy} - Current is carrier charge density times mobility times the remaining cross-section times the local field; W_ch is the device width and the 2 counts both halves.
V_P = \frac{q N_D a^{2}}{2\varepsilon_s} - Define pinch-off as the bias at which W reaches a, so the channel is fully depleted. Solve the first line for that condition.
I_D \int_0^L dy = 2 q N_D \mu W_{ch}\int_0^{V_{DS}}\left[a - W(V)\right] dV - Current is the same at every point in steady state, so it is a constant, the variables separate and both sides integrate.
I_D = I_{DSS}\left(1-\frac{V_{GS}}{V_P}\right)^{2} - Evaluate at the onset of saturation and collect the constants into I_DSS. The square comes from the square root in W combined with the integration.

A square-law transfer characteristic whose controlling parameter V_P is set entirely by doping and channel thickness - both fixed at fabrication, which is why V_P is a device constant rather than a bias-dependent quantity.

Pinch-off voltage: V_P = \frac{q N_D a^{2}}{2\varepsilon_s} - a is the channel half-thickness. Doping and geometry alone set it, both fixed at fabrication.
Depletion width: W(V) = \sqrt{\frac{2\varepsilon_s (V_{bi}-V_{GS}+V)}{q N_D}} - Grows with reverse bias, which is the whole control mechanism.
Zero-bias current: I_{DSS} = I_D \big|_{V_{GS}=0} - Drain current with the gate shorted to the source - the maximum for a depletion device.
Transconductance: g_m = \frac{2 I_{DSS}}{|V_P|}\left(1-\frac{V_{GS}}{V_P}\right) - Differentiate the Shockley expression with respect to V_GS.

Take a silicon JFET channel with N_D = 1e16 cm^-3 and half-thickness a = 0.5 um. Then V_P is about (1.602e-19 x 1e16 x (0.5e-4)^2) divided by (2 x 1.04e-12), roughly 1.9 V in magnitude. With I_DSS = 10 mA, a gate bias of -1 V gives I_D = 10 x (1 - 1/1.9)^2, about 2.2 mA. Note the sign discipline: for an n-channel JFET V_P is negative in the usual convention, so check whether a datasheet quotes the magnitude before substituting.

A JFET datasheet gives V_GS(off) = -4 V. What drain current should you expect at V_GS = 0 V, and what does that mean for a circuit that powers up with the gate undriven?

At V_GS = 0 the device passes I_DSS, its maximum current - it is fully on. A depletion-mode device with a floating or undriven gate conducts hard at power-up, so a circuit relying on the transistor being off until software drives it will instead see full current through the load the moment the rail comes up.

3. HEMT: separate the carriers from the dopants

Doping a channel to make it conduct carries a built-in penalty: the ionised dopant atoms that supply the carriers are also the impurities that scatter them, so raising the carrier density lowers the mobility. A high-electron-mobility transistor escapes the trade by putting the dopants in one layer and the carriers in another. A wide-bandgap barrier layer is doped; the electrons it releases fall into the narrower-bandgap material next to it and collect in a triangular potential well at the interface. They are then spatially separated from the ionised donors they came from, so they keep a mobility far closer to that of undoped material.

The carriers that collect at that interface are confined to a sheet a few nanometres thick, thin enough that motion perpendicular to the interface is quantised. This is the two-dimensional electron gas, described by a sheet density in carriers per square centimetre rather than a volume concentration. In the AlGaN/GaN system used for RF and power devices there is a further effect: the materials are piezoelectric and spontaneously polarised, so a 2DEG forms at the interface even with no intentional doping at all. That is why GaN HEMTs are normally-on devices unless deliberate steps are taken to deplete the channel at zero bias.

That last point has a consequence worth stating plainly. A normally-on power device conducts when its gate driver is unpowered, which is exactly the condition during a supply brown-out or before a controller has booted. Commercial GaN power parts therefore either use a p-type gate to lift the threshold above zero, or pair a normally-on HEMT with a low-voltage silicon MOSFET in a cascode so the composite behaves as a normally-off device. Both are engineering answers to a physics default, and knowing which one a part uses tells you how it will behave when its driver rail collapses.

First-order relation

n_s = \frac{\varepsilon_b}{q\,d}\left(V_{GS}-V_{TH}\right)

Derivation: Show that the 2DEG behaves as a charge-control channel whose barrier plays the role of a gate oxide.

The barrier layer is fully depleted and carries no free carriers of its own.
The 2DEG is thin compared with the barrier thickness, so it can be treated as a sheet of charge at the interface.
V_TH already absorbs the Schottky barrier height, the conduction-band discontinuity and any polarisation charge.

C_b = \frac{\varepsilon_b}{d} - The depleted barrier between the gate and the 2DEG is a parallel-plate capacitor of thickness d.
Q_s = C_b\,(V_{GS}-V_{TH}) - Charge control across that capacitor: gate voltage above threshold induces sheet charge in the well.
Q_s = q\,n_s - The induced sheet charge is carried by electrons, so dividing by the elementary charge converts it to a sheet density.
n_s = \frac{\varepsilon_b}{q\,d}\,(V_{GS}-V_{TH}) - Combine the previous three lines. The barrier permittivity over its thickness has taken exactly the place C_ox occupies in a MOSFET, which is the whole point: the electrostatics are the same and only the transport differs.
R_{sh} = \frac{1}{q\,n_s\,\mu} - Sheet resistance of a two-dimensional conducting layer follows from its sheet carrier density and its mobility.

The barrier is a gate dielectric in every respect that matters to the electrostatics, so a HEMT obeys the same charge-control law as a MOSFET. The advantage lives entirely in the mobility term, which modulation doping keeps high.

2DEG sheet density: n_s = \frac{\varepsilon_b}{q\,d}(V_{GS}-V_{TH}) - d is the barrier thickness. The barrier is the gate dielectric in all but name.
Sheet resistance: R_{sh} = \frac{1}{q\,n_s\,\mu} - Ohms per square - the figure of merit for a 2DEG channel.
Drain current: I_D = q\,n_s\,\mu\,\frac{W}{L}\,V_{DS} - The same charge-control law as lesson 1, with n_s in place of C_g times overdrive.
Cutoff frequency: f_T = \frac{g_m}{2\pi C_{gs}} - Why high mobility and a short gate matter: both raise g_m relative to the gate capacitance.

An AlGaN/GaN HEMT with a 20 nm barrier of relative permittivity about 9 gives a gate capacitance per area of 9 x 8.854e-14 divided by 20e-7, roughly 0.4 uF/cm^2. With 3 V of overdrive that is 1.2 uC/cm^2, so n_s is about 7.5e12 cm^-2. At a 2DEG mobility of 1500 cm^2/(V.s) the sheet resistance is 1/(1.602e-19 x 7.5e12 x 1500), about 555 ohms per square. Bulk GaN doped to the same carrier density would scatter far more and give a substantially lower mobility.

Why does a HEMT achieve both a high carrier density and a high mobility, when doping a bulk channel forces a trade between the two?

Because the carriers and the dopants are in different layers. The donors sit in the wide-bandgap barrier while the electrons collect in the well on the other side of the interface, so the carriers are spatially separated from the ionised impurities that would otherwise scatter them. The density is set by the barrier and the gate, and the mobility stays close to that of undoped material.

4. Geometry as the design variable: FinFET, GAAFET and power devices

When a planar MOSFET is made short enough, the drain starts to compete with the gate for control of the channel potential. The gate sits above the channel while the drain depletion region reaches in from the side, and once the two are comparable the threshold falls with drain voltage, the subthreshold slope degrades and the device leaks. Thinning the oxide helps, but gate tunnelling eventually forbids it. The remaining variable is geometry: wrap the gate around more of the channel and the gate wins the competition again. That single idea produced the FinFET, whose gate covers three sides of a thin vertical fin, and the gate-all-around nanosheet, whose gate covers all four.

Wrapping the gate has a consequence that changes how a circuit is designed. In a planar device the channel width is a drawn dimension and can take any value. In a FinFET the width is the perimeter of the fin, so it comes in quanta of one fin, and sizing a gate means choosing an integer number of fins rather than a continuous width. Nanosheet devices restore some of that freedom because the sheet width can be drawn, which is one of the reasons the industry moved to them. The electrostatic argument behind all of it is captured by the natural length: the smaller it is relative to the channel length, the better the gate controls the channel.

Power devices answer a different constraint with the same tool. A power MOSFET must hold off hundreds of volts, which needs a thick lightly doped drift region, and that region dominates the on-resistance - the trade between blocking voltage and conduction loss is a hard material limit for silicon. Vertical constructions such as VDMOS and trench devices route current down through the wafer to use area efficiently. The superjunction goes further: alternating p and n pillars deplete each other sideways, so the drift region can be doped far more heavily for the same blocking voltage, which breaks the conventional silicon limit rather than merely approaching it. LDMOS keeps the structure lateral so it can be integrated alongside logic.

First-order relation

\lambda = \sqrt{\frac{\varepsilon_s}{\varepsilon_{ox}}\,t_{si}\,t_{ox}}

Derivation: Show why thinning the body and wrapping the gate both improve short-channel electrostatics, through the natural length.

A fully depleted body of thickness t_si with a gate oxide of thickness t_ox.
A parabolic approximation to the potential across the body thickness - the standard scale-length analysis.
Drain influence decays along the channel with a single characteristic length.

\frac{\partial^{2}\psi}{\partial x^{2}} + \frac{\partial^{2}\psi}{\partial y^{2}} = -\frac{\rho}{\varepsilon_s} - Two-dimensional Poisson equation in the channel. The second term is exactly what a one-dimensional long-channel analysis throws away.
\psi(x,y) \approx \psi_s(y) + c_1(y)\,x + c_2(y)\,x^{2} - Parabolic approximation across the body thickness, with boundary conditions set by the gate oxide on one side and the buried side on the other.
\frac{d^{2}\psi_s}{dy^{2}} - \frac{\psi_s - \psi_{long}}{\lambda^{2}} = 0 - Substituting the parabola into Poisson and applying the oxide boundary condition collapses the problem to one dimension with a single length constant.
\lambda = \sqrt{\frac{\varepsilon_s}{\varepsilon_{ox}}\,t_{si}\,t_{ox}} - That length constant is fixed by body thickness, oxide thickness and the permittivity ratio - nothing else.
\psi_s - \psi_{long} \propto e^{-y/\lambda} - The solution decays exponentially, so drain influence penetrates a distance of order lambda into the channel.
W_{eff} = n_{fin}\,(2H_{fin}+T_{fin}) - For a fin the gated perimeter replaces the drawn width, which is what makes device width quantised.

Short-channel control improves whenever lambda shrinks relative to L. Thinning the body, thinning the oxide, raising the gate permittivity and gating more sides all shrink it - which is the list of things the industry did, in that order.

FinFET effective width: W_{eff} = n_{fin}\,(2 H_{fin} + T_{fin}) - Width is quantised in fins, so sizing means choosing an integer.
Natural length: \lambda = \sqrt{\frac{\varepsilon_s}{\varepsilon_{ox}}\,t_{si}\,t_{ox}} - Gate control holds while L is several times lambda. Multi-gate geometries shrink it.
Drift resistance: R_{drift} = \frac{W_d}{q\,\mu_n\,N_D\,A} - Why a thick, lightly doped blocking layer costs conduction loss.
Silicon limit: R_{on}A \propto BV^{2.5} - The conventional drift-region trade-off: on-resistance rises steeply with blocking voltage.
Superjunction: R_{on}A \propto BV\,W_{p} - Charge-balanced pillars make the exponent nearly linear; W_p is the pillar pitch.

A fin 6 nm thick and 50 nm tall has an effective width of 2 x 50 + 6 = 106 nm per fin. Doubling the drive of such a device means two fins, 212 nm, and there is nothing available in between. For the natural length, a fully depleted body with t_si = 6 nm and t_ox = 1 nm gives lambda = sqrt((11.7/3.9) x 6 x 1) nm, about 4.2 nm - so a 20 nm channel is roughly five natural lengths and the gate keeps control.

A planar transistor and a FinFET are drawn with the same channel length. Why does the FinFET have a steeper subthreshold slope and less drain-induced barrier lowering?

Because the gate surrounds the channel on three sides rather than one, and the fin body is thin enough for the gate to control its potential throughout. That shrinks the natural length, so the drain's depletion region reaches a smaller fraction of the way into the channel. The gate keeps control of the barrier, so the threshold shifts less with drain voltage and the subthreshold slope stays closer to the thermal floor.

The FET Family

1. One charge-control law, four ways to build the gate

Derivation: Show that one charge-control expression covers every family, so the differences reduce to two parameters.

Two devices are both called FETs and both have a gate. Why can one of them be destroyed by a forward gate bias that the other tolerates?

2. JFET and MESFET: the gate is a reverse-biased diode

Derivation: Derive the Shockley square-law relation for a JFET from the depletion width that controls the channel.

A JFET datasheet gives V_GS(off) = -4 V. What drain current should you expect at V_GS = 0 V, and what does that mean for a circuit that powers up with the gate undriven?

3. HEMT: separate the carriers from the dopants

Derivation: Show that the 2DEG behaves as a charge-control channel whose barrier plays the role of a gate oxide.

Why does a HEMT achieve both a high carrier density and a high mobility, when doping a bulk channel forces a trade between the two?

4. Geometry as the design variable: FinFET, GAAFET and power devices

Derivation: Show why thinning the body and wrapping the gate both improve short-channel electrostatics, through the natural length.

A planar transistor and a FinFET are drawn with the same channel length. Why does the FinFET have a steeper subthreshold slope and less drain-induced barrier lowering?

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