CMOS & VLSI

MOSFET Derivations

Where the formulae come from: the gradual-channel integration, threshold and body effect, small-signal parameters, and the subthreshold floor.

Reviewed 2026-08-223,834 words

1. Drain current, derived from the gradual channel approximation

The square law is usually presented as a result to memorise, which hides the fact that it is three lines of calculus resting on one geometric assumption. That assumption is the gradual channel approximation: the vertical field from the gate is much stronger than the lateral field from the drain, so each thin slice of the channel can be solved as an independent one-dimensional MOS capacitor. Once that is granted, the inversion charge at any point depends only on the local gate-to-channel voltage, and everything after it is integration.

The integration matters because it produces the term most people misremember. The channel is not uniform: the voltage along it rises from zero at the source to V_DS at the drain, so the local overdrive falls as you move toward the drain and the inversion charge thins out with it. Integrating that varying charge from source to drain is what produces the V_DS squared over two term. It is not a correction bolted on afterwards; it is a direct consequence of the channel being tapered, and a derivation that omits it is describing a uniform resistor rather than a transistor.

Saturation then arrives without any new mechanism. The triode expression is a downward parabola in V_DS, and differentiating it shows the peak sits exactly where the drain-end overdrive reaches zero. Beyond that point the model has no channel left to describe, so the current is held at its peak value and the square law falls out by substitution. That is the honest account: saturation in this model is where the equation stops being valid, and the flat characteristic is a statement about the model as much as about the device.

First-order relation

I_D = \frac{\mu_n C_{ox}}{2}\frac{W}{L}(V_{GS}-V_T)^{2}

Derivation: Derive the triode and saturation drain-current expressions for a long-channel NMOS.

Gradual channel approximation: the vertical field dominates the lateral field, so each slice solves as a one-dimensional MOS capacitor.
Charge-sheet approximation: the inversion layer has negligible thickness.
Constant mobility, independent of both vertical and lateral field.
Drift transport only; diffusion is negligible above threshold.
Uniform substrate doping, so V_T does not vary along the channel. Source and body both at 0 V.

V_{GC}(y) = V_{GS}-V(y) - The gate-to-channel voltage at position y is reduced by the channel potential V(y), which rises from 0 at the source to V_DS at the drain.
|Q_{inv}(y)| = C_{ox}\left[V_{GS}-V_T-V(y)\right] - Charge control applied locally: only the part of the gate-to-channel voltage above threshold supports mobile charge.
I_D = W\,|Q_{inv}(y)|\,v(y) - Current equals charge per unit area, times the channel width, times the carrier drift velocity.
v(y) = \mu_n E(y) = \mu_n \frac{dV}{dy} - Low-field drift with constant mobility; the field along the channel is the gradient of the channel potential.
I_D = \mu_n C_{ox} W \left[V_{GS}-V_T-V(y)\right]\frac{dV}{dy} - Substitute the charge and velocity expressions into the current expression.
I_D \int_0^{L} dy = \mu_n C_{ox} W \int_0^{V_{DS}} \left[V_{GS}-V_T-V\right] dV - In steady state no charge accumulates, so I_D is the same at every y. That makes it a constant and the variables separate.
I_D = \mu_n C_{ox}\frac{W}{L}\left[(V_{GS}-V_T)V_{DS}-\frac{V_{DS}^{2}}{2}\right] - Evaluate both integrals. The squared term comes from integrating V dV - it is the tapering of the channel.
\frac{\partial I_D}{\partial V_{DS}} = \mu_n C_{ox}\frac{W}{L}\left[(V_{GS}-V_T)-V_{DS}\right] = 0 - Find the peak of the parabola, which is where the model reaches its own boundary.
V_{DS,sat} = V_{GS}-V_T - Solve the previous line. This is exactly the condition for drain-end inversion charge to reach zero.
I_D = \frac{\mu_n C_{ox}}{2}\frac{W}{L}(V_{GS}-V_T)^{2} - Substitute V_DS,sat back into the triode expression; the two terms collapse into one half of the square.

One integration produces both regions and the boundary between them. The square law is not a separate model - it is the triode expression evaluated at the point where the channel runs out.

Triode region: I_D = \mu_n C_{ox}\frac{W}{L}\left[(V_{GS}-V_T)V_{DS}-\frac{V_{DS}^{2}}{2}\right] - Valid while V_DS stays below the overdrive.
Saturation boundary: V_{DS,sat} = V_{GS}-V_T - Where the parabola peaks and drain-end inversion charge reaches zero.
Saturation region: I_D = \frac{\mu_n C_{ox}}{2}\frac{W}{L}(V_{GS}-V_T)^{2} - Substitute the boundary into the triode expression.
On-resistance: R_{on} = \frac{1}{\mu_n C_{ox}\frac{W}{L}(V_{GS}-V_T)} - The slope at the origin - the number a switch design actually needs.
Process transconductance: k' = \mu_n C_{ox} - Everything the process fixes, separated from everything the designer draws.

With k' = 200 uA/V^2, W/L = 10, V_T = 0.4 V and V_GS = 1.0 V, the overdrive is 0.6 V. In saturation I_D = (200e-6/2) x 10 x 0.36 = 360 uA. At V_DS = 0.2 V the device is in triode instead: I_D = 200e-6 x 10 x (0.6 x 0.2 - 0.02) = 200 uA. Dropping the V_DS squared term would have given 240 uA - a 20 percent overestimate at only a third of the saturation voltage.

The triode expression is a downward parabola in V_DS, so it predicts the current falls again once V_DS exceeds the overdrive. Why does a real device not do that?

Because the derivation stops being valid at that point. It assumes a continuous inversion channel from source to drain, and at V_DS equal to the overdrive the drain-end inversion charge reaches zero, so there is no channel left to integrate over. Beyond it the carriers are swept across a short depleted region by drift, the current stays at its peak value, and the falling branch of the parabola describes nothing physical.

2. Threshold voltage and the body effect, from electrostatics

Threshold voltage looks like a single physical property and is actually a sum of three separate accounting entries. The gate must first overcome the built-in offset between the gate material and the substrate together with any charge trapped in the oxide - that is the flat-band voltage, a process constant that cannot be computed from geometry. It must then bend the surface bands far enough to invert them. Finally it must supply the charge that terminates the field lines from the depletion region underneath. Adding those three gives the threshold expression, and each term fails in a different way when a process changes.

The definition of strong inversion is a convention rather than a physical edge. It is taken as the point where the surface potential reaches twice the Fermi potential, which is where the electron density at the surface equals the hole density in the bulk. Nothing switches on there: the inversion charge grows exponentially through the transition, and it is that exponential tail, not the threshold, that decides how well a transistor turns off. Treating the convention as a hard boundary is the usual reason a hand-calculated threshold disagrees with an extracted one, since extraction methods differ in exactly where on the curve they place the line.

The body effect follows immediately from the same electrostatics. Reverse-biasing the source relative to the substrate means the surface must bend by the extra source-body voltage as well as the usual amount, which widens the depletion region and increases the depletion charge the gate has to support. The threshold therefore rises. This is not a second-order correction in a stacked circuit: the upper device in a series stack sits with its source above the substrate, so its threshold is raised and its drive reduced, and that is the physical reason a tall NAND stack performs worse than its transistor count suggests.

First-order relation

V_T = V_{T0} + \gamma\left(\sqrt{2\phi_F+V_{SB}}-\sqrt{2\phi_F}\right)

Derivation: Derive the zero-bias threshold voltage, then the body-effect expression, from MOS electrostatics.

Uniform substrate doping N_A - so no halo or retrograde implant.
Depletion approximation: the depleted region contains only ionised acceptors and has a sharp edge.
Strong inversion defined by the convention that surface potential equals twice the Fermi potential.
Inversion charge is negligible compared with depletion charge at the threshold point itself.

\phi_F = \frac{kT}{q}\ln\frac{N_A}{n_i} - Definition of the bulk Fermi potential for a p-type substrate.
\psi_s = 2\phi_F - The strong-inversion convention: the surface is inverted as strongly as the bulk is doped.
\frac{d^{2}\psi}{dx^{2}} = \frac{q N_A}{\varepsilon_s} - Poisson's equation in the depleted region, where the only charge is the ionised acceptors.
W_{dep} = \sqrt{\frac{2\varepsilon_s\,\psi_s}{q N_A}} - Integrate Poisson twice, applying zero field at the depletion edge and surface potential psi_s at the surface.
|Q_{dep}| = q N_A W_{dep} = \sqrt{2 q \varepsilon_s N_A \psi_s} - Charge per unit area in the depleted region, substituting the width from the previous line.
V_{GS} = V_{FB} + \psi_s + \frac{|Q_{dep}|}{C_{ox}} - The applied gate voltage divides into the flat-band offset, the surface band bending, and the voltage dropped across the oxide to support the depletion charge.
V_{T0} = V_{FB} + 2\phi_F + \frac{\sqrt{2 q \varepsilon_s N_A (2\phi_F)}}{C_{ox}} - Evaluate at the strong-inversion condition. This is the threshold with source and body at the same potential.
\psi_s = 2\phi_F + V_{SB} - Reverse-biasing the source relative to the body means the surface must bend by that much more before inverting.
V_T = V_{FB}+2\phi_F+\frac{\sqrt{2q\varepsilon_s N_A (2\phi_F+V_{SB})}}{C_{ox}} - Repeat the same derivation with the new surface potential, measuring the gate voltage from the source.
V_T = V_{T0} + \gamma\left(\sqrt{2\phi_F+V_{SB}}-\sqrt{2\phi_F}\right) - Subtract the zero-bias case and collect the constants into gamma.

Threshold is the sum of a process offset, a band-bending term and an oxide term - and the body effect is what happens when the third term grows because the surface has further to bend.

Fermi potential: \phi_F = \frac{kT}{q}\ln\frac{N_A}{n_i} - How far the bulk Fermi level sits from intrinsic. About 0.35 to 0.45 V for typical doping.
Depletion width: W_{dep} = \sqrt{\frac{2\varepsilon_s(2\phi_F)}{q N_A}} - At the onset of strong inversion.
Depletion charge: |Q_{dep}| = \sqrt{2 q \varepsilon_s N_A (2\phi_F)} - Per unit area. The gate must supply an equal and opposite charge.
Zero-bias threshold: V_{T0} = V_{FB} + 2\phi_F + \frac{\sqrt{2q\varepsilon_s N_A(2\phi_F)}}{C_{ox}} - Flat band, plus band bending, plus the oxide drop.
Body factor: \gamma = \frac{\sqrt{2 q \varepsilon_s N_A}}{C_{ox}} - Rises with substrate doping and with oxide thickness.

With N_A = 1e17 cm^-3 and n_i = 1e10 cm^-3, phi_F = 0.0259 x ln(1e7) = 0.417 V, so 2 phi_F = 0.835 V. Then |Q_dep| = sqrt(2 x 1.602e-19 x 1.04e-12 x 1e17 x 0.835) = 1.67e-7 C/cm^2. With t_ox = 3 nm, C_ox = 1.15e-6 F/cm^2, so the depletion term contributes 0.145 V. gamma = sqrt(2 x 1.602e-19 x 1.04e-12 x 1e17) divided by 1.15e-6 = 0.16 V^0.5, and 1 V of source-body bias raises V_T by 0.16 x (sqrt(1.835) - sqrt(0.835)) = 0.071 V.

In a four-input NAND stack, why is the transistor nearest the output slower than the one nearest ground, even though all four are drawn identically?

Because its source is not at the substrate potential. The devices below it hold its source above ground, which creates a source-to-body reverse bias, widens the depletion region beneath it and raises its threshold voltage. A higher threshold means less overdrive for the same gate voltage and therefore less drive current, and the penalty grows with each device further up the stack.

3. Small signal: transconductance, output resistance and intrinsic gain

A transistor used as an amplifier is described by how much its output current changes for a small change at its input, and how much it resists changes at its output. Those two derivatives are transconductance and output resistance, and they come from differentiating the large-signal expressions rather than from any new physics. In digital terms the same two quantities have different names: transconductance is drive strength, and output resistance is how flat the saturation characteristic is, which decides whether a logic level droops under load.

Transconductance has three algebraically equivalent forms, and choosing between them is not cosmetic - each answers a different design question. Written in terms of overdrive it says what widening the device buys at fixed voltage. Written as twice the drain current over the overdrive it says how much transconductance a given current is buying. Written as a square root of the current it says that at fixed current, widening the device raises transconductance only as the square root of the width. That last form is the reason brute-force widening stops paying, and it is the most useful of the three.

Output resistance in this model comes from channel-length modulation. Beyond saturation, additional drain voltage widens the pinched region, which shortens the effective channel and lets the current creep up. The empirical lambda factor captures it well enough for hand analysis and poorly enough that it should never be extrapolated: lambda is extracted by fitting, it scales roughly inversely with channel length, and real output conductance has several contributing mechanisms. The product of transconductance and output resistance is the intrinsic gain, the most a single device can deliver, and it falls as devices get shorter.

First-order relation

g_m = \frac{\partial I_D}{\partial V_{GS}} = \sqrt{2\mu_n C_{ox}\frac{W}{L} I_D}

Derivation: Obtain the small-signal parameters by differentiating the saturation expression, and show the three forms of g_m are one quantity.

The device is biased in saturation and stays there for the whole small-signal excursion.
The square-law long-channel expression describes the large-signal behaviour.
Channel-length modulation is modelled by the empirical factor (1 + lambda V_DS), with lambda small.

I_D = \frac{\mu_n C_{ox}}{2}\frac{W}{L}(V_{GS}-V_T)^{2}(1+\lambda V_{DS}) - Saturation expression from lesson 1, with the empirical output-conductance factor attached.
g_m \equiv \frac{\partial I_D}{\partial V_{GS}} = \mu_n C_{ox}\frac{W}{L}(V_{GS}-V_T) - Differentiate with respect to gate voltage, dropping the lambda term as a small correction.
g_m = \frac{2 I_D}{V_{GS}-V_T} - Divide the previous line by the saturation expression and rearrange - the overdrive squared cancels down to one power.
V_{GS}-V_T = \sqrt{\frac{2 I_D}{\mu_n C_{ox} (W/L)}} - Solve the saturation expression for the overdrive at a known current.
g_m = \sqrt{2\mu_n C_{ox}\frac{W}{L} I_D} - Substitute that overdrive into the current form. Width now appears under a square root.
r_o = \left(\frac{\partial I_D}{\partial V_{DS}}\right)^{-1} = \frac{1}{\lambda I_D} - Differentiate with respect to drain voltage; only the lambda factor depends on it, then invert.
A_v = g_m r_o = \frac{2 I_D}{V_{GS}-V_T}\cdot\frac{1}{\lambda I_D} = \frac{2}{\lambda (V_{GS}-V_T)} - Multiply the two. The bias current cancels, so intrinsic gain depends on overdrive and lambda alone.

Intrinsic gain is independent of both width and current, and improves only by lowering the overdrive or lengthening the channel. That is why analogue designers use long devices at low overdrive and digital designers do the opposite.

Transconductance: g_m = \mu_n C_{ox}\frac{W}{L}(V_{GS}-V_T) - Direct differentiation of the square law.
Current form: g_m = \frac{2 I_D}{V_{GS}-V_T} - The same quantity, expressed at a known bias current.
Square-root form: g_m = \sqrt{2\mu_n C_{ox}\frac{W}{L}\,I_D} - At fixed current, g_m rises only as the square root of the width.
Output resistance: r_o = \frac{1}{\lambda I_D} - From channel-length modulation. Lambda scales roughly as 1/L.
Intrinsic gain: A_v = g_m r_o = \frac{2}{\lambda (V_{GS}-V_T)} - The ceiling for one device - independent of width, and falling as devices shorten.
Body transconductance: g_{mb} = \frac{\gamma\,g_m}{2\sqrt{2\phi_F+V_{SB}}} - The body acts as a second, weaker gate - typically 10 to 30 percent of g_m.

Take I_D = 100 uA with an overdrive of 0.2 V. Then g_m = 2 x 100e-6 / 0.2 = 1 mS. With lambda = 0.1 per volt, r_o = 1/(0.1 x 100e-6) = 100 kohm, so the intrinsic gain is 1e-3 x 1e5 = 100. Now hold the current fixed and quadruple W/L: g_m only doubles, to 2 mS, because it follows the square root of the width - while the gate capacitance you have to drive has gone up fourfold.

At a fixed bias current, why does making a transistor four times wider only double its transconductance?

Because at fixed current, widening the device lowers the overdrive it needs to carry that current. Transconductance in the current form is twice the current divided by the overdrive, so as the overdrive falls the transconductance rises - but the overdrive scales as the inverse square root of the width, so the transconductance follows the square root of the width rather than the width itself.

4. Subthreshold conduction, the 60 mV/decade floor and velocity saturation

Below threshold a transistor does not switch off; it becomes exponential. The surface is weakly inverted, the barrier between source and channel is lowered gradually by the gate, and carriers cross it by diffusion rather than drift. The current therefore falls by a fixed factor for each fixed decrement of gate voltage, and the rate at which it falls is the single most important number in low-power design. It is called the subthreshold swing, and it has a floor that no amount of process work can beat while conduction is over a thermal barrier.

That floor comes from a capacitive divider. The gate does not control the surface potential completely: the depletion capacitance beneath the channel steals part of every gate-voltage change, so the surface potential moves by only a fraction of what is applied. That fraction is the body factor, and it multiplies the thermal voltage in the swing expression. At room temperature the ideal limit is about 60 mV per decade and a real device manages 70 to 90, which means turning a transistor off by six orders of magnitude costs roughly half a volt of gate swing that could otherwise have been supply headroom.

That number is why voltage scaling stopped. Supply must stay well above threshold for speed, and threshold must stay high enough that an off device leaks acceptably - and the 60 mV floor is what stops threshold from scaling down with supply. At the other end of the characteristic, velocity saturation removes the reward for raising the supply: above a critical field the carriers stop accelerating, drive current becomes linear in overdrive rather than quadratic, and it stops depending on channel length. Between the two effects, both ends of the square-law intuition fail on a modern node.

First-order relation

S = \frac{dV_{GS}}{d(\log_{10} I_D)} = n\,\frac{kT}{q}\ln 10

Derivation: Derive the subthreshold swing and its temperature-set floor, then show what velocity saturation does to drive current.

Weak inversion: inversion charge is small compared with depletion charge, and transport is by diffusion.
Boltzmann statistics for the carrier population, which is what makes the exponential exact.
The surface potential responds to the gate through a linear capacitive divider.

n_s \propto \exp\left(\frac{q\psi_s}{kT}\right) - Boltzmann statistics: carrier density at the surface depends exponentially on how far the bands have bent.
\frac{d\psi_s}{dV_{GS}} = \frac{C_{ox}}{C_{ox}+C_{dep}} = \frac{1}{n} - Capacitive divider between the oxide and the depletion capacitance below it - only part of a gate change reaches the surface.
I_D \propto \exp\left(\frac{q V_{GS}}{n k T}\right) - Combine the previous two lines: the gate controls the surface potential through 1/n, and the current follows the surface potential exponentially.
\ln I_D = \frac{q V_{GS}}{n k T} + \text{const} - Take the natural logarithm of both sides to linearise the relationship.
\frac{d(\log_{10} I_D)}{dV_{GS}} = \frac{q}{n k T \ln 10} - Convert to base-10 logarithm, since swing is quoted per decade.
S = \frac{dV_{GS}}{d(\log_{10} I_D)} = n\frac{kT}{q}\ln 10 - Invert the previous line. This is the swing, and n is bounded below by 1.
S_{min} = \frac{kT}{q}\ln 10 \approx 59.5\ \mathrm{mV/decade} - Set n = 1, the perfect-gate-control limit, at 300 K. Nothing in this chain depends on the process.
v = \frac{\mu E}{1+E/E_{sat}} - Empirical velocity-field relation: linear at low field, saturating at high field.
E = \frac{V_{DS}}{L} \gg E_{sat} \Rightarrow v \to v_{sat} - In a short channel the same drain voltage produces a much larger lateral field, so carriers reach the saturation velocity.
I_{D,sat} = W\,C_{ox}(V_{GS}-V_T)\,v_{sat} - Substitute the saturated velocity into the charge-times-velocity current expression. Both the square and the length dependence are gone.

Two hard limits at opposite ends of the characteristic. Turn-off is bounded by thermal statistics at about 60 mV per decade, and turn-on stops rewarding extra voltage once carriers reach saturation velocity.

Subthreshold current: I_D \propto \exp\left(\frac{q(V_{GS}-V_T)}{n k T}\right) - Exponential in gate voltage, which is why turn-off is gradual rather than abrupt.
Drain saturation: 1-\exp\left(-\frac{q V_{DS}}{kT}\right) - The factor that makes subthreshold current flatten once V_DS exceeds a few kT/q, about 100 mV.
Body factor: n = 1 + \frac{C_{dep}}{C_{ox}} - How much of a gate-voltage change actually reaches the surface. Ideally 1.
Subthreshold swing: S = n\,\frac{kT}{q}\ln 10 - About 60 mV/decade at 300 K when n = 1; 70 to 90 in practice.
Velocity saturation: v = \frac{\mu E}{1+E/E_{sat}} - Linear at low field, saturating near 1e7 cm/s in silicon.
Short-channel drive: I_{D,sat} \approx W C_{ox} v_{sat}(V_{GS}-V_T) - Linear in overdrive, and independent of channel length.

At 300 K, kT/q = 25.85 mV, so kT/q times ln 10 = 59.5 mV per decade with n = 1. A device with C_dep/C_ox = 0.4 has n = 1.4 and S = 83 mV/decade, so five decades of turn-off need 417 mV of gate swing. At 125 C the thermal voltage rises to 34.3 mV, S becomes 110 mV/decade, and the same five decades now need 552 mV - on top of the threshold having fallen. That compounding is what makes hot standby leakage so much worse than a room-temperature measurement suggests.

Why can a process engineer not simply improve the subthreshold swing below 60 mV per decade at room temperature?

Because it is set by thermodynamics rather than by the process. Conduction is by carriers crossing a barrier and their energy distribution is thermal, so the population above any barrier height falls by a factor of e for each kT/q of barrier height. That fixes the best possible swing at kT/q times ln 10, about 60 mV per decade at 300 K. Process work can push the body factor toward one, but it cannot get below the thermal limit while the transport mechanism is thermionic.

MOSFET Derivations

1. Drain current, derived from the gradual channel approximation

Derivation: Derive the triode and saturation drain-current expressions for a long-channel NMOS.

The triode expression is a downward parabola in V_DS, so it predicts the current falls again once V_DS exceeds the overdrive. Why does a real device not do that?

2. Threshold voltage and the body effect, from electrostatics

Derivation: Derive the zero-bias threshold voltage, then the body-effect expression, from MOS electrostatics.

In a four-input NAND stack, why is the transistor nearest the output slower than the one nearest ground, even though all four are drawn identically?

3. Small signal: transconductance, output resistance and intrinsic gain

Derivation: Obtain the small-signal parameters by differentiating the saturation expression, and show the three forms of g_m are one quantity.

At a fixed bias current, why does making a transistor four times wider only double its transconductance?

4. Subthreshold conduction, the 60 mV/decade floor and velocity saturation

Derivation: Derive the subthreshold swing and its temperature-set floor, then show what velocity saturation does to drive current.

Why can a process engineer not simply improve the subthreshold swing below 60 mV per decade at room temperature?

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