CMOS & VLSI

The Real Four-Terminal MOSFET

The device you actually get: four terminals, body diodes, five gate capacitances that move with operating region, series resistance and temperature.

Reviewed 2026-08-223,447 words

1. Four terminals, and why source and drain are not fixed labels

The schematic symbol has three terminals in most textbook drawings and the device has four. The body is a real electrical terminal, not a drawing convention: it sets the threshold through the body effect, it forms a junction diode with each of the source and the drain, and it provides the return path for substrate current. In a discrete power MOSFET the manufacturer ties the body to the source internally, which is why the part has three pins and why it has a body diode from drain to source that appears in every application note. On an integrated die the body is shared with every other device in the same well, and that shared connection is the one designers forget.

Source and drain are also not properties of the silicon. The two diffusions are very nearly symmetric - the same implant, the same anneal, mirror images either side of the channel - and the terminal that is acting as the source is decided by the bias, not by the layout. For an n-channel device the source is whichever of the two sits at the lower potential, because that is the terminal supplying electrons into the channel. Swap the voltages and the roles swap with them. Symmetry does break in real processes, through asymmetric halo implants or drain-extension structures designed for high voltage, but the default assumption should be symmetry.

This is not pedantry, because it explains a behaviour that otherwise looks like the threshold changing. Consider an NMOS pass transistor charging a node from zero. At the start the output is the low terminal, so it is the source. As the output rises past the input it becomes the high terminal, and the other side becomes the source instead. The gate-to-source voltage that controls the device is now measured against a terminal that is climbing, so the overdrive collapses and the device stops conducting a threshold below the gate. Nothing about the transistor changed - the terminal its control voltage is referenced to did.

First-order relation

V_{GS} = V_G - \min(V_1,V_2)\quad(\text{n-channel})

Derivation: Find the highest voltage a bare NMOS pass transistor can deliver, including the body effect.

The gate is held at a fixed voltage while the output node charges.
The body is tied to ground while the source rises with the output.
Conduction stops when the gate-to-source voltage falls to the threshold.

S = \text{output node} - While the output is the lower of the two terminals it is acting as the source, which is the terminal the control voltage is measured against.
V_{GS} = V_G - V_{out} - Gate-to-source voltage with the source at the output potential, which is rising as the node charges.
\text{conduction stops when } V_{GS} = V_T - Below threshold the channel current becomes exponentially small, so charging effectively halts.
V_{SB} = V_{out} - 0 = V_{out} - The body is at ground, so the source-to-body reverse bias equals the output voltage itself.
V_T(V_{out}) = V_{T0}+\gamma\left(\sqrt{2\phi_F+V_{out}}-\sqrt{2\phi_F}\right) - Substitute that bias into the body-effect expression - the threshold rises as the output rises.
V_{out,max} = V_G - V_{T0}-\gamma\left(\sqrt{2\phi_F+V_{out,max}}-\sqrt{2\phi_F}\right) - Set the two conditions equal. The result is implicit, because the limit appears on both sides.

The maximum output is below the gate voltage by more than the zero-bias threshold, and the shortfall grows as the output rises. The transmission gate exists precisely to avoid this: a parallel PMOS passes the high level with no such limit.

Source identification: S = \arg\min(V_1,V_2)\ \text{for NMOS},\quad \arg\max\ \text{for PMOS} - The terminal supplying carriers, decided instant by instant.
Body diodes: D\!-\!B\ \text{and}\ S\!-\!B - Two junction diodes that must stay reverse biased. In a discrete part, the S-B one is shorted out.
Threshold drop: V_{out,max} = V_{G}-V_T(V_{SB}) - Why a bare NMOS pass gate cannot deliver a full high level.
Body effect on a pass gate: V_{SB}\uparrow \Rightarrow V_T\uparrow \Rightarrow V_{out,max}\downarrow - The loss compounds: as the output rises, the threshold that limits it rises too.

An NMOS with V_T0 = 0.4 V, gamma = 0.3 and 2 phi_F = 0.8 V has its gate at 1.8 V and passes a signal to a node starting at 0 V. Ignoring body effect the output would stop at 1.4 V. But at that output the source-to-body bias is 1.4 V, so V_T = 0.4 + 0.3 x (sqrt(2.2) - sqrt(0.8)) = 0.60 V, and the output actually stops near 1.2 V. Solving self-consistently matters, because the threshold that limits the output depends on the output.

A discrete power MOSFET datasheet shows a diode from drain to source that is not in the integrated device's schematic. Where does it come from?

From the body. Each of the source and drain diffusions forms a pn junction with the body, and in a discrete part the manufacturer ties the body to the source internally so the package can have three pins. That short-circuits the source-body junction and leaves the drain-body junction exposed between drain and source - the body diode. It conducts whenever the drain goes below the source, which is what makes these parts usable in bridge circuits.

2. Where the five capacitances come from, and how they move with region

A MOSFET has five capacitances that a designer must account for, and they are not fixed values. Between the gate and the other three terminals there are C_gs, C_gd and C_gb; between each diffusion and the body there are C_db and C_sb. The gate capacitances have two distinct origins: an overlap component, which is geometric and comes from the gate extending slightly over the diffusions, and a channel component, which exists only when there is a channel and is shared out between terminals according to where that channel reaches.

That sharing is what changes with operating region, and the change is dramatic even though the total barely moves. In cutoff there is no channel, so nothing screens the gate from the substrate and the whole channel-area capacitance appears as C_gb, leaving only overlap on the source and drain. Once a channel forms it screens the body completely, so C_gb collapses to nearly zero. In the linear region the channel reaches both ends, so its charge splits evenly between source and drain. In saturation the drain end is pinched off and the gate no longer controls it, so C_gd falls back to overlap alone and roughly two thirds of the channel charge is attributed to the source.

The junction capacitances behave differently again, because they are reverse-biased diodes rather than a controlled channel. Each has a bottom-plate component proportional to the diffusion area and a sidewall component proportional to its perimeter, and both fall as the reverse bias widens the depletion region - so they are nonlinear, and a single number is a linearised approximation over an assumed swing. This is why diffusion sharing between adjacent transistors is worth real effort in layout: merging two diffusions into one island removes an entire area and two sidewalls from the node.

First-order relation

C_{gs}^{sat} = \tfrac{2}{3}C_{ox}WL + C_{ov},\qquad C_{gd}^{sat} = C_{ov}

Derivation: Derive the Miller-multiplied input capacitance and show why a small C_gd dominates.

The stage is inverting with small-signal voltage gain of magnitude A_v.
Input and output move together in time, so the gain applies instantaneously.
C_gd is a linear capacitance over the swing considered.

v_{out} = -A_v\,v_{in} - Definition of an inverting stage with gain magnitude A_v.
\Delta v_{gd} = v_{in}-v_{out} = v_{in}(1+A_v) - The voltage across C_gd is the difference between its plates, and they move in opposite directions.
q_{gd} = C_{gd}\,v_{in}(1+A_v) - Charge on the capacitor is its capacitance times the voltage across it.
C_{in,eff} = \frac{q_{gd}}{v_{in}} = C_{gd}(1+A_v) - Effective capacitance seen at the input is the charge the input must supply per volt of input change.
C_{in} = C_{gs} + C_{gd}(1+A_v) - Add the gate-source part, whose other plate is not moving, so it is not multiplied.

A capacitance bridging input and output is charged through the sum of both swings, so it costs the driver far more than its value suggests. A 0.2 fF overlap in a stage with gain 10 loads the input like 2.2 fF.

Cutoff: C_{gb}=C_{ox}WL,\quad C_{gs}=C_{gd}=C_{ov} - No channel, so the gate couples straight through to the body.
Linear: C_{gs}=C_{gd}=\tfrac{1}{2}C_{ox}WL+C_{ov},\quad C_{gb}\approx 0 - The channel reaches both ends and screens the body.
Saturation: C_{gs}=\tfrac{2}{3}C_{ox}WL+C_{ov},\quad C_{gd}=C_{ov} - The drain end is pinched off, so the gate sees only overlap there.
Overlap: C_{ov} = C_{ov}'\,W - Geometric, present in every region, and increasingly dominant as channels shorten.
Junction capacitance: C_j = \frac{C_{j0}A}{(1+V_R/\phi_0)^{m}} + \frac{C_{jsw0}P}{(1+V_R/\phi_0)^{m_{sw}}} - Area plus sidewall, both falling with reverse bias. Nonlinear, so datasheet values are linearised.
Miller effect: C_{in} = C_{gs} + (1+|A_v|)\,C_{gd} - Why the smallest gate capacitance often dominates the input load.

Take C_ox = 10 fF/um^2, W = 1 um, L = 0.1 um and an overlap of 0.2 fF/um. The channel capacitance is 1 fF. In cutoff, C_gb = 1 fF with 0.2 fF on each of source and drain. In saturation, C_gs = 0.67 + 0.2 = 0.87 fF while C_gd is just 0.2 fF. Now put that device in an inverting stage with a gain of 10: the input sees C_gs + 11 x C_gd = 0.87 + 2.2 = 3.07 fF, so the smallest of the two gate capacitances contributes more than twice what the largest does.

The total gate capacitance changes little between cutoff and saturation, yet the load a driving stage sees changes a great deal. Why?

Because what matters is not the total but which terminal each part is connected to. In cutoff most of it sits between gate and body, which is a quiet node, so the driver sees little beyond overlap. In saturation most of it sits between gate and source, and the remaining gate-drain part is Miller multiplied by the stage gain because the drain swings the opposite way. The same few femtofarads present a completely different load depending on where the other plate is and what it is doing.

3. Series resistance, and what the ideal model leaves at the terminals

The drain-current equations describe the channel, and the terminals are not the channel. Between the contact and the edge of the channel lies the diffusion itself, the silicide on top of it, and the contacts through to metal - each contributing resistance in series with the device. Historically this was a small correction. As channels shortened it stopped being one: the channel resistance falls as devices shrink while the contact and diffusion resistance does not shrink with it, so the parasitic term is now a substantial fraction of the total in a modern device.

Series resistance does two things, and the second is easy to miss. The obvious effect is that it drops voltage, so the channel sees less than the applied drain-to-source voltage and the device delivers less current than the equations predict. The subtler effect is degeneration at the source: any current through the source resistance raises the internal source potential, which reduces the gate-to-source voltage that actually controls the channel. The device partly turns itself off as it conducts, which flattens the transfer characteristic and reduces the effective transconductance.

Gate resistance is a separate concern that matters at speed rather than in DC. The gate electrode is a strip of silicide over polysilicon or metal, resistive along its length, and it drives a distributed capacitance along that same length - which makes the gate an RC transmission line rather than an equipotential plate. Wide devices are therefore laid out as several parallel fingers contacted at both ends rather than one long strip, because the effective gate resistance of a distributed structure falls with the square of the number of fingers.

First-order relation

g_{m,eff} = \frac{g_m}{1+g_m R_S}

Derivation: Derive the degenerated transconductance and show it is a negative feedback result.

Small-signal operation around a bias point in saturation.
The intrinsic device obeys i_d = g_m v_gs with the internal source node.
R_S is a linear resistance carrying the full drain current.

v_{gs,int} = v_{in} - i_d R_S - The internal source rises by the drop across R_S, so the control voltage is what is left of the input after that.
i_d = g_m\,v_{gs,int} - The intrinsic device responds to the voltage at its own terminals, not the external ones.
i_d = g_m(v_{in}-i_d R_S) - Substitute the first line into the second - the output current now appears on both sides.
i_d(1+g_m R_S) = g_m v_{in} - Collect the i_d terms. This is the standard negative-feedback form.
g_{m,eff} = \frac{i_d}{v_{in}} = \frac{g_m}{1+g_m R_S} - Divide through. The loop gain g_m R_S is what divides the transconductance down.

Source resistance is negative feedback, so it reduces transconductance by one plus the loop gain - and in exchange it makes the result less dependent on the device's own g_m, which is why degeneration is used deliberately for linearity.

Source degeneration: g_{m,eff} = \frac{g_m}{1+g_m R_S} - Current through R_S lifts the internal source, cutting the overdrive that controls the channel.
Effective drain voltage: V_{DS,int} = V_{DS}-I_D(R_S+R_D) - The channel sees less than the terminals do.
Contact-dominated resistance: R_{SD} = R_{sheet}\frac{L_{diff}}{W} + \frac{R_c}{N_{contacts}} - Why contacts are multiplied rather than enlarged.
Distributed gate resistance: R_{g,eff} = \frac{R_{sheet}}{3}\frac{W}{L}\ \text{(one end)} - The factor of three comes from the distributed RC; contacting both ends gives twelve.
Finger scaling: R_{g,eff} \propto \frac{1}{N_f^{2}} - One factor from shorter fingers, one from parallel connection - which is why wide devices are fingered.

A device with g_m = 5 mS and 20 ohms of source resistance has an effective transconductance of 5e-3 / (1 + 5e-3 x 20) = 4.55 mS, a 9 percent loss before anything else is considered. For the gate, a 10 um wide device with 0.1 um length and 10 ohms per square of gate sheet resistance contacted at one end gives R_g = (10/3) x (10/0.1) = 333 ohms. Split into ten 1 um fingers contacted at both ends and it falls by roughly a factor of 100, to a few ohms.

Why does source series resistance reduce transconductance, when drain series resistance mostly just drops voltage?

Because the source is the reference for the control voltage. Current flowing through source resistance raises the internal source potential above the terminal, and the gate-to-source voltage that actually controls the channel is measured against that internal node - so the overdrive shrinks as the current grows, and the device partially turns itself off. Drain resistance sits outside the control loop; it drops voltage but does not feed back on the controlling terminal.

4. What heating a MOSFET does, and why the answers conflict

Temperature moves three device parameters at once and they do not move in the same direction, which is why the effect on a circuit is not obvious from any single one. Mobility falls, because lattice vibrations scatter carriers more strongly, and that reduces drive current. Threshold voltage falls, roughly two millivolts per degree, because the Fermi potential shrinks as intrinsic carrier concentration rises - and that increases drive current. Leakage rises steeply, because the subthreshold exponent contains kT and the threshold is falling at the same time, so both factors push the same way.

For drive current the two effects compete and which wins depends on the supply voltage. At a comfortable overdrive, the mobility loss dominates and a hot chip is slower - the familiar result, and the reason the slow corner is specified hot. At low supply voltage, where the overdrive is a small fraction of the threshold, the threshold shift dominates instead and a hot chip is actually faster. That sign reversal is called temperature inversion, it is routine on modern low-voltage nodes, and it invalidates the old assumption that the hot corner is always the slow one - a timing signoff that checks only hot may miss the real worst case.

Leakage has no such ambiguity. It rises steeply and monotonically, roughly doubling for every ten degrees over the usual range, and the resulting power raises the temperature further. That feedback loop is thermal runaway, and it is a genuine failure mode rather than a theoretical concern: a chip whose cooling is marginal can enter a state where leakage heats it, the heat increases leakage, and the process does not stop until something throttles or fails. It is also why leakage measured at room temperature tells you very little about standby power in a hot enclosure.

First-order relation

\mu(T) = \mu_0\left(\frac{T}{T_0}\right)^{-1.5},\qquad \frac{dV_T}{dT}\approx -2\ \mathrm{mV/K}

Derivation: Find the condition under which raising temperature speeds a device up rather than slowing it down.

Long-channel saturation, so drive current is proportional to mobility times overdrive squared.
Mobility follows a power law in absolute temperature and threshold falls linearly with it.
Supply voltage and gate drive are held constant while temperature changes.

I_D \propto \mu(T)\,(V_{GS}-V_T(T))^{2} - Saturation drive current, with both temperature-dependent factors made explicit.
\frac{1}{I_D}\frac{dI_D}{dT} = \frac{1}{\mu}\frac{d\mu}{dT} + \frac{2}{V_{ov}}\left(-\frac{dV_T}{dT}\right) - Take the logarithmic derivative, which turns a product into a sum of fractional rates.
\frac{1}{\mu}\frac{d\mu}{dT} = -\frac{1.5}{T} - Differentiate the mobility power law - the fractional rate depends only on absolute temperature.
\frac{1}{I_D}\frac{dI_D}{dT} = -\frac{1.5}{T} + \frac{2|\kappa|}{V_{ov}} - Substitute both rates, with kappa the magnitude of the threshold drift.
\frac{2|\kappa|}{V_{ov}} > \frac{1.5}{T} \Rightarrow \frac{dI_D}{dT} > 0 - Set the sum positive. Current rises with temperature when the threshold term beats the mobility term.
V_{ov} < \frac{2|\kappa|T}{1.5} - Rearrange for the overdrive below which the inversion occurs - a smaller overdrive makes it more likely.

With kappa around 2 mV/K at 350 K the crossover overdrive is roughly 0.9 V, so any circuit operating below about that overdrive is in the temperature-inverted regime. That is most modern low-voltage logic, which is why the assumption that hot means slow no longer holds.

Mobility: \mu(T)=\mu_0\left(\frac{T}{T_0}\right)^{-1.5} - Phonon scattering. The exponent is empirical and varies with doping.
Threshold drift: V_T(T) = V_{T0}+\kappa\,(T-T_0),\quad \kappa\approx-2\ \mathrm{mV/K} - Falls with temperature, because the Fermi potential shrinks.
Leakage: I_{leak}(T) \approx I_0\,2^{(T-T_0)/10} - Roughly doubling per ten degrees - a rule of thumb, not a physical law.
Thermal runaway: \frac{dP_{leak}}{dT}\,R_{th} > 1 - The loop-gain condition. Once satisfied, temperature climbs until something intervenes.
Junction temperature: T_j = T_a + P\,R_{th,ja} - The equation that connects the electrical budget to the mechanical one.

Take a device at 25 C moved to 125 C. Mobility scales by (398/298)^-1.5, about 0.65 - so a 35 percent loss of drive from that term alone. The threshold falls by 2 mV x 100 = 0.2 V, which at an overdrive of 0.6 V is a 33 percent increase in overdrive and nearly cancels it. Leakage, meanwhile, scales by 2^10, about a thousandfold. Two of the three effects roughly cancel and the third does not, which is the whole story of modern power management in one calculation.

Timing signoff traditionally treats the hot corner as the slow one. On a low-voltage node that assumption can be wrong. Why?

Because two temperature effects compete. Rising temperature lowers mobility, which slows the device, and lowers threshold voltage, which speeds it up. At a healthy overdrive the mobility term dominates and hot is slow. At low supply the overdrive is small, so a fixed threshold shift is a large relative change in overdrive, and the threshold term wins instead - the device is faster hot and slower cold. Signing off only at the hot corner then misses the real worst case, which is cold.

The Real Four-Terminal MOSFET

1. Four terminals, and why source and drain are not fixed labels

Derivation: Find the highest voltage a bare NMOS pass transistor can deliver, including the body effect.

A discrete power MOSFET datasheet shows a diode from drain to source that is not in the integrated device's schematic. Where does it come from?

2. Where the five capacitances come from, and how they move with region

Derivation: Derive the Miller-multiplied input capacitance and show why a small C_gd dominates.

The total gate capacitance changes little between cutoff and saturation, yet the load a driving stage sees changes a great deal. Why?

3. Series resistance, and what the ideal model leaves at the terminals

Derivation: Derive the degenerated transconductance and show it is a negative feedback result.

Why does source series resistance reduce transconductance, when drain series resistance mostly just drops voltage?

4. What heating a MOSFET does, and why the answers conflict

Derivation: Find the condition under which raising temperature speeds a device up rather than slowing it down.

Timing signoff traditionally treats the hot corner as the slow one. On a low-voltage node that assumption can be wrong. Why?

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