Static CMOS, Complex Gates & Pass Logic

Chapter 7. Static CMOS Gates and Complex Logic

7.1 Pull-up/pull-down duality

Static complementary CMOS implements a logic function with an NMOS pull-down network and a dual PMOS pull-up network. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is Series in one network maps to parallel in the dual; F = NOT(PDN conduction condition). Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

Series in one network maps to parallel in the dual; F = NOT(PDN conduction condition).

The design consequence is concrete: Build the PDN from the conditions that should force zero, then form the PUN by De Morgan duality. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. Size each device in a 3-high series stack relative to a unit inverter NMOS so the first-order path resistance is similar.

Solution. Resistance scales inversely with width and series values add. Body effect, internal charge, diffusion capacitance, and legal layout require characterization.

Wstack / Wunit ≈ number in series = 3

1. Which approximation in the relation for pull-up/pull-down duality is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

7.2 NAND and NOR sizing

Series devices weaken a path through resistance, body effect, and internal-node charge; parallel branches increase diffusion capacitance. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is A k-stack often starts near k times unit width for equal resistance, then is corrected by characterization. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

A k-stack often starts near k times unit width for equal resistance, then is corrected by characterization.

The design consequence is concrete: NAND is generally friendlier than NOR in CMOS because stacked NMOS devices outperform equivalently stacked PMOS at equal pitch. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. Size each device in a 4-high series stack relative to a unit inverter NMOS so the first-order path resistance is similar.

Solution. Resistance scales inversely with width and series values add. Body effect, internal charge, diffusion capacitance, and legal layout require characterization.

Wstack / Wunit ≈ number in series = 4

1. Which approximation in the relation for nand and nor sizing is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

7.3 Compound gates and factoring

AOI/OAI gates implement factored logic in one stage, reducing intermediate capacitance and often improving delay and energy. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is AB+CD maps naturally to an AOI structure followed by polarity planning. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

AB+CD maps naturally to an AOI structure followed by polarity planning.

The design consequence is concrete: Transistor count is not the only metric: input pin capacitance, stack depth, diffusion sharing, and output inversion matter. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. Size each device in a 2-high series stack relative to a unit inverter NMOS so the first-order path resistance is similar.

Solution. Resistance scales inversely with width and series values add. Body effect, internal charge, diffusion capacitance, and legal layout require characterization.

Wstack / Wunit ≈ number in series = 2

1. Which approximation in the relation for compound gates and factoring is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

7.4 Static hazards and reconvergent paths

Unequal path delays can briefly create the wrong Boolean value when multiple inputs or reconvergent signals change. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is A static-1 hazard in SOP logic can be removed by a consensus term when the timing contract requires it. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

A static-1 hazard in SOP logic can be removed by a consensus term when the timing contract requires it.

The design consequence is concrete: Synchronous designs often tolerate internal glitches if they settle before capture, but glitches still consume power and can escape through enables. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. Size each device in a 3-high series stack relative to a unit inverter NMOS so the first-order path resistance is similar.

Solution. Resistance scales inversely with width and series values add. Body effect, internal charge, diffusion capacitance, and legal layout require characterization.

Wstack / Wunit ≈ number in series = 3

1. Which approximation in the relation for static hazards and reconvergent paths is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

7.5 Ratioed and pass-transistor contrasts

Pseudo-NMOS, transmission-gate, and pass-transistor families trade transistor count against static current, swing, robustness, and restoration. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is Ratioed logic requires pull-up/pull-down strength constraints; an NMOS pass device loses a strong logic one. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

Ratioed logic requires pull-up/pull-down strength constraints; an NMOS pass device loses a strong logic one.

The design consequence is concrete: Use non-complementary styles deliberately at bounded interfaces, not as a casual transistor-count shortcut. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. Size each device in a 4-high series stack relative to a unit inverter NMOS so the first-order path resistance is similar.

Solution. Resistance scales inversely with width and series values add. Body effect, internal charge, diffusion capacitance, and legal layout require characterization.

Wstack / Wunit ≈ number in series = 4

1. Which approximation in the relation for ratioed and pass-transistor contrasts is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

Chapter 8. Transmission Gates, Muxes, and Level Restoration

8.1 Single pass devices

An NMOS passes a strong zero but a degraded one; a PMOS passes a strong one but a degraded zero because conduction ends as overdrive collapses. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is NMOS high limit is roughly V_G-|V_TN(V_SB)|. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

NMOS high limit is roughly V_G-|V_TN(V_SB)|.

The design consequence is concrete: Pass devices are bilateral switches at the circuit level, so source/drain naming follows instantaneous voltage rather than a permanent physical role. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. An effective conducting path of 2.5 kΩ drives 24 fF. Estimate the 50% transition delay.

Solution. Use a lumped RC estimate, then account for voltage-dependent resistance, input slew, charge sharing, and distributed capacitance in transient verification.

t₅₀ ≈ 0.69RC = 41.4 ps

1. Which approximation in the relation for single pass devices is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

8.2 Complementary transmission gate

Parallel NMOS and PMOS controlled by complementary enables pass both rails with lower, flatter resistance. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is R_TG(V) = R_n(V) || R_p(V). Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

R_TG(V) = R_n(V) || R_p(V).

The design consequence is concrete: The two device conductances complement each other near opposite rails; break-before-make timing may still be required in bus switches. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. An effective conducting path of 4.0 kΩ drives 40 fF. Estimate the 50% transition delay.

Solution. Use a lumped RC estimate, then account for voltage-dependent resistance, input slew, charge sharing, and distributed capacitance in transient verification.

t₅₀ ≈ 0.69RC = 110.4 ps

1. Which approximation in the relation for complementary transmission gate is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

8.3 Multiplexers and XOR

Transmission gates implement compact multiplexers and parity structures, often with fewer series devices than static CMOS. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is Y = S D_1 + NOT(S) D_0. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

Y = S D_1 + NOT(S) D_0.

The design consequence is concrete: Local complementary controls and restoration inverters determine whether the apparent transistor saving survives in a full system. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. An effective conducting path of 1.5 kΩ drives 16 fF. Estimate the 50% transition delay.

Solution. Use a lumped RC estimate, then account for voltage-dependent resistance, input slew, charge sharing, and distributed capacitance in transient verification.

t₅₀ ≈ 0.69RC = 16.6 ps

1. Which approximation in the relation for multiplexers and xor is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

8.4 Charge sharing and leakage retention

Disconnected internal nodes retain charge only through capacitance and lose it through subthreshold, junction, gate, and coupling paths. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is Delta V = (C_1/(C_1+C_2))(V_1-V_2) for ideal charge sharing. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

Delta V = (C_1/(C_1+C_2))(V_1-V_2) for ideal charge sharing.

The design consequence is concrete: Keeper devices trade retention and noise immunity against contention and delay. Their ratio is a functional parameter. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. An effective conducting path of 2.5 kΩ drives 24 fF. Estimate the 50% transition delay.

Solution. Use a lumped RC estimate, then account for voltage-dependent resistance, input slew, charge sharing, and distributed capacitance in transient verification.

t₅₀ ≈ 0.69RC = 41.4 ps

1. Which approximation in the relation for charge sharing and leakage retention is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

8.5 Level restoration and cascading

A degraded pass level can cause static current in the next CMOS gate; a restoring inverter or full transmission gate returns legal rails. At transistor level, follow the causal chain from terminal bias to charge distribution, electric field, carrier motion, and observable voltage or current. That chain identifies which node stores state, which boundary supplies charge, and why supply, temperature, geometry, or initial condition can move a result that a Boolean abstraction treats as fixed.

The useful first-order relation is Require V_pass >= V_IH and V_pass <= V_IL with margin at all corners. Declare polarities, current directions, units, and operating region before substitution. After calculation, check the assumed region and a limiting case. The expression should remain consistent with charge conservation and topology as a voltage, capacitance, resistance, or device strength approaches an extreme.

Require V_pass >= V_IH and V_pass <= V_IL with margin at all corners.

The design consequence is concrete: Cascading threshold-dropping stages compounds uncertainty, body effect, and delay, so restoration boundaries should be intentional. Compare the sensitivity of the desired metric with the penalties paid in input capacitance, diffusion, leakage, area, noise, reliability, and verification burden. Then propagate the choice into the driving stage, receiving stage, interconnect, power network, and physical layout. A local improvement is useful only when the system-level margin also improves.

Worked example

Problem. An effective conducting path of 4.0 kΩ drives 40 fF. Estimate the 50% transition delay.

Solution. Use a lumped RC estimate, then account for voltage-dependent resistance, input slew, charge sharing, and distributed capacitance in transient verification.

t₅₀ ≈ 0.69RC = 110.4 ps

1. Which approximation in the relation for level restoration and cascading is most likely to fail first in a scaled technology?
2. Design a two-sweep experiment that distinguishes the intended mechanism from a parasitic or measurement artifact.

CMOS: The Two Networks Every Gate Is Made Of

A CMOS gate is two complementary transistor networks between the supply rails: PMOS above pulling the output high, NMOS below pulling it low, arranged so exactly one of them conducts for any input. That complementarity is why CMOS draws almost no current when it is not switching, and it is the reason digital electronics scaled. It also explains a fact the schematic hides: the inverting gates are the primitives, and AND and OR cost more than NAND and NOR rather than less.

How it is built

• PMOS conducts when its gate is low and NMOS conducts when its gate is high. Putting them in complementary networks means one path is always off, so there is no static path from supply to ground and no steady current.
• Series in one network is parallel in the other. A NAND has its NMOS transistors in series - all inputs high to pull low - and its PMOS in parallel, and a NOR is the exact mirror.
• AND is a NAND followed by an inverter, and OR is a NOR followed by one. There is no cheaper construction, because a non-inverting CMOS network is not possible directly - the complementary structure inherently inverts.
• A NOR is worse than a NAND at the same input count, because its series transistors are PMOS and hole mobility is roughly half that of electrons. Standard-cell libraries reflect this: NAND-based logic is generally faster.
• Series stacks degrade more than linearly. Each transistor adds resistance and the body effect raises the threshold of the ones further from the rail, which is why gates wider than about four inputs are built as trees.
• A transmission gate is a PMOS and NMOS in parallel used as a switch rather than as logic. It passes both levels well where a single transistor passes one poorly, and it is how multiplexers and XOR gates are usually built.

Design procedure

1. Count transistors before assuming a structure is cheap. AND-OR logic on a schematic is NAND-NAND on the die, and the transistor count is what decides area.
2. Prefer NAND-based structures over NOR-based ones where speed matters, because the series stack is NMOS rather than PMOS.
3. Keep series stacks shallow. Above four inputs, build a tree of smaller gates rather than one wide cell.
4. Size transistors for the load, remembering that PMOS must be wider than NMOS for symmetric rise and fall - roughly two to one in most processes.
5. Use transmission gates for pass structures such as multiplexers, and remember they do not restore a level - a chain of them degrades the signal and needs a buffer.
6. Check that no input can leave both networks off, which floats the output, or both on, which is a short from supply to ground.

Key terms

Pull-up network

PMOS transistors connecting the output to the supply.

Pull-down network

NMOS transistors connecting the output to ground.

Complementary

Exactly one network conducts, so there is no static current path.

Series / parallel duality

Series in one network is parallel in the other.

Body effect

Threshold rising for transistors further from the rail in a stack.

Transmission gate

PMOS and NMOS in parallel as a switch. Passes both levels well.

Mobility ratio

Holes are roughly half as mobile as electrons, so PMOS must be wider.

Worked example

A two-input NAND is four transistors: two PMOS in parallel to the supply and two NMOS in series to ground. If either input is low, one PMOS conducts and the output goes high; only when both are high does the NMOS series path complete and pull the output low. Adding an inverter to make an AND costs two more transistors and one more gate delay. That is the whole reason a synthesised netlist is full of NANDs and inverters rather than the ANDs and ORs the designer wrote.

Common pitfalls

More in CMOS & VLSI

• Silicon PhysicsSemiconductor foundations, junctions, MOS electrostatics, NMOS/PMOS operation, compact models, and scaled-device nonidealities.
• Layout & SignoffESD, latch-up, back-powering, stick diagrams, DRC/LVS/PEX, PVT, characterization, constraints, and STA.
• Timing & PowerRC delay, logical effort, interconnect, crosstalk, dynamic and short-circuit power, leakage, and glitches.
• Inverter DesignThe voltage-transfer curve, switching threshold, noise margins, sizing, capacitance, delay, and transition behavior.
• Sequential & CDCLatches, flip-flops, setup and hold, clocking, metastability, synchronizers, handshakes, and multi-bit crossings.
• Memory Circuits6T SRAM operation and margins, array periphery, DRAM sensing and refresh, and Flash storage mechanisms.
• I/O & PDNI/O pads, level shifting, open-drain buses, simultaneous switching, ground bounce, decoupling, and PDN behavior.
• BenchcraftMeasurement loading, bandwidth, grounding, current and thermal observation, fault isolation, and evidence capture.
• Scaling FrontierDennard scaling, leakage and power walls, variability, FinFET quantization, and gate-all-around devices.
• Course MapThe complete learning map: ten focused areas, 22 chapters, 110 lessons, worked examples, exercises, references, and progress tracking.
• CMOS & VLSIA curated silicon curriculum from energy bands and the MOS capacitor through gates, timing, power, memory, I/O, reliability, layout, signoff, FinFETs and GAAFETs—with 110 lessons, worked calculations, bench notes, progress tracking, and transistor-level labs.