CMOS & VLSI

Dynamic CMOS & Domino

Precharge and evaluate, domino cascading, charge sharing and keepers - the fast logic family, and the honest account of why it faded.

Reviewed 2026-08-223,483 words

1. Precharge and evaluate: computing with stored charge

A static CMOS gate has two complementary networks, and the pull-up network is the expensive half - it needs a PMOS for every input, and PMOS devices must be wide because holes are slow. A dynamic gate deletes it. In its place sits a single PMOS driven by the clock, which pulls the output node to the supply while the clock is low. That is the precharge phase, and no logic happens during it. When the clock goes high the precharge device turns off, a single NMOS at the bottom of the stack turns on, and the pull-down network either discharges the output or leaves it alone. That is the evaluate phase, and it is where the logic happens.

The saving is real and substantial. An n-input function needs n plus two transistors instead of the 2n a static gate needs, and more importantly the input capacitance is one NMOS gate per input rather than an NMOS and a wide PMOS - typically less than half. The output is driven only by NMOS devices, which are the fast ones. For a wide function such as a 64-bit comparator or an address decoder, where the static version needs a stack of enormous PMOS transistors, the difference in both area and speed is large enough to have justified the entire family.

The cost is that the output is not held. During evaluate, a node that was not discharged is floating at the supply with nothing driving it - its value is charge on a capacitor, retained only by the absence of any path to remove that charge. Every problem in the rest of this primer follows from that one property. Subthreshold leakage removes the charge slowly, charge sharing redistributes it suddenly, coupled noise injects into it, and none of these matter in a static gate because a static gate is always actively driven from one rail or the other.

First-order relation

t_{hold} \approx \frac{C_L\,\Delta V}{I_{leak}}

Derivation: Find the minimum clock frequency a dynamic node can tolerate before leakage corrupts it.

The undischarged node is floating with only leakage current removing charge.
Leakage is approximately constant over the small droop considered.
The downstream gate misreads the node once it falls by more than its noise margin.

I_{leak} = -C_L\frac{dV}{dt} - Current leaving a capacitor is its capacitance times the rate its voltage falls.
\Delta V = \frac{I_{leak}}{C_L}\,t - Integrate with leakage treated as constant, which holds while the droop is small.
\Delta V < NM_H - The requirement: the node must not fall by more than the receiving gate's high noise margin.
t_{hold} = \frac{C_L\,NM_H}{I_{leak}} - Solve for the time at which the margin is exhausted.
f_{min} = \frac{1}{t_{hold}} = \frac{I_{leak}}{C_L\,NM_H} - The clock must return to precharge within that time, which sets a floor on frequency.
I_{leak}(T)\uparrow \Rightarrow f_{min}\uparrow - Leakage roughly doubles per ten degrees, so the minimum frequency climbs steeply with temperature.

A dynamic gate has a minimum operating frequency as well as a maximum, and the minimum is set by leakage and therefore by temperature. Static logic has no lower bound at all, which is why it can be clock-gated, stopped and single-stepped.

Transistor count: N_{dyn} = n+2 \quad\text{vs}\quad N_{static} = 2n - One clocked precharge, one clocked evaluate, and the pull-down network only.
Retention time: t_{hold} = \frac{C_L\,\Delta V_{max}}{I_{leak}} - How long a floating high level survives. Sets a minimum clock frequency.
Precharge time: t_{pre} \approx 0.69\,R_{pre}C_L - The node must reach the rail before evaluate begins, which bounds the duty cycle.
Evaluate delay: t_{eval} \approx \frac{C_L V_{DD}/2}{I_{Dn}} - Set by the NMOS stack alone - no PMOS in the switching path.

Take a dynamic node with C_L = 20 fF at 1 V that must not droop more than 200 mV, leaking 50 nA. Retention is 20e-15 x 0.2 / 50e-9, about 80 us - so the clock must not stop for longer than that, which rules out clock gating and single-stepping a debugger. At 125 C the leakage is perhaps a thousand times higher and retention falls to 80 ns, which is a handful of cycles. The circuit that worked on a cold bench fails in a hot enclosure.

A dynamic gate has no pull-up network, yet its output goes high. What drives it there, and what holds it there?

The clocked precharge PMOS drives it high, but only during the precharge phase while the clock is low. During evaluate nothing holds it - the high level is charge stored on the node capacitance, retained only because no conducting path exists to remove it. That is why a dynamic node has a retention time and a minimum clock frequency, and why a static gate has neither.

2. Domino: the cascading problem and its fix

Dynamic gates cannot be connected directly to one another, and the reason is a timing race rather than a logic error. At the end of precharge every dynamic node in a chain is high. When evaluate begins, a first-stage gate that should discharge its output takes a finite time to do so - and during that time its output is still high, so the second-stage gate sees a high input and begins discharging its own node. When the first stage finally falls, the second stage's input goes away, but the charge it has already removed does not come back. The second node is left at a wrong, partially discharged level with no way to recover until the next precharge.

Domino logic fixes it with one component: a static inverter on the output of every dynamic gate. Now the signal presented to the next stage is the inverse of the dynamic node, so at the start of evaluate it is low rather than high. Every input to every downstream gate begins low and can only rise, which means no downstream gate can be falsely triggered - a gate only ever evaluates once its inputs have genuinely arrived. The transitions ripple through the chain in order, which is where the name comes from.

The constraint this imposes is monotonicity, and it is severe. Every input to a dynamic gate must make at most one transition during evaluate, and it must be low to high. That means the pull-down networks can only implement functions of uninverted inputs, so domino logic cannot directly build anything requiring an inversion in the middle of a chain - no XOR, no arbitrary function. The standard answers are to push inversions to the boundaries using De Morgan, or to carry both polarities of every signal through the chain, which doubles the wiring and the transistor count and eats much of the original saving.

First-order relation

\text{inputs must be monotonically rising during evaluate}

Derivation: Show how much charge a non-monotonic input steals, and why it is unrecoverable.

The downstream dynamic node is precharged to the supply and then floating.
A glitching input turns the pull-down network on for a time t_g before going away.
The pull-down conducts an approximately constant current while on.

Q_{lost} = \int_0^{t_g} i_{pd}\,dt \approx I_{pd}\,t_g - Charge removed is the discharge current integrated over the time the false path is conducting.
\Delta V = \frac{Q_{lost}}{C_L} = \frac{I_{pd}t_g}{C_L} - That charge came off the node capacitance, so the node voltage falls by charge over capacitance.
\text{no path restores } Q_{lost} \text{ during evaluate} - The precharge device is off for the whole evaluate phase, so nothing can put the charge back.
V_{node} = V_{DD}-\frac{I_{pd}t_g}{C_L}\ \text{until next precharge} - The droop persists for the rest of the cycle - it is a stored error, not a transient.
\text{fails when } \frac{I_{pd}t_g}{C_L} > NM_H - Once the droop exceeds the receiving gate's noise margin the wrong logic value is propagated.

A glitch of any duration removes charge permanently, because a floating node has no restoring path. This is the structural reason for the monotonicity rule - it is not a guideline but a correctness requirement.

Domino stage: \text{dynamic gate} \to \text{static inverter} \to \text{next dynamic gate} - The inverter is what makes cascading safe, at the cost of one static stage per level.
Monotonicity: 0 \to 1\ \text{only, at most once per evaluate} - The rule every domino input must satisfy. Violating it corrupts the node irreversibly.
Footed evaluate: N_{footed} = n+2 - An evaluate NMOS in series prevents any discharge path during precharge.
Footless: N_{footless} = n+1 - Drops the evaluate device - faster and smaller, but only safe when inputs are guaranteed low during precharge.
Dual-rail cost: N_{dual} \approx 2(n+2) - The price of non-monotonic functions: carry both polarities through the whole chain.

Consider two dynamic gates connected directly, both precharged to 1 V, with the first taking 30 ps to discharge. For those 30 ps the second gate sees a high input and discharges at, say, 20 uA into 15 fF - removing 0.6e-15 coulombs, which is 40 mV. The second node is now at 960 mV instead of 1 V, and the error is permanent until precharge. Repeat over a chain of six stages and the accumulated droop is well past the receiving gate's noise margin.

Why does a footless domino gate work at all, given that its pull-down network has a direct path to ground with no evaluate transistor?

Because in a domino chain its inputs are guaranteed low during precharge - they come from the static inverters of preceding domino stages, whose dynamic nodes are precharged high, so the inverter outputs are low. With every input low the pull-down network cannot conduct, so no evaluate device is needed to prevent it. The guarantee comes from the surrounding structure rather than from the gate, which is why footless gates cannot be used at the start of a chain where inputs come from elsewhere.

3. Charge sharing and the keeper

The output node is not the only capacitance in a dynamic gate. Every internal node in the pull-down stack has its own junction and gate capacitance, and those nodes are left wherever the previous cycle left them - often discharged. When evaluate begins and a partial input pattern turns on some of the stack but not all of it, the output node is connected to those internal capacitances without being connected to ground. Charge redistributes between them until they reach a common voltage, and the output falls even though no discharge path to ground was ever completed.

It is a pure charge-conservation problem and the arithmetic is simple, which makes the danger easy to underestimate. The final voltage is the original charge divided by the total capacitance now sharing it, so the droop depends on the ratio of internal to output capacitance. In a tall stack with a small output load - exactly the configuration that motivated dynamic logic in the first place, since deep functions were where it won - that ratio can approach one, and the output can fall by a third or more from charge sharing alone. The gate produces a wrong answer with every transistor working exactly as designed.

The keeper is the standard fix: a small PMOS from the supply to the output node, with its gate driven by the domino inverter's output, so it turns on precisely when the node is high and supplies enough current to replace what leakage and charge sharing remove. Its size is a genuine trade-off rather than a free improvement. Too weak and it cannot hold the node against leakage at temperature; too strong and it fights the pull-down network during a legitimate evaluate, slowing the gate and in the worst case preventing the discharge entirely - a contention failure. Keeper sizing is a ratioed-logic problem living inside a family that was supposed to be ratioless.

First-order relation

V_{final} = V_{DD}\,\frac{C_L}{C_L+C_{int}}

Derivation: Derive the shared voltage and the keeper size needed to survive it.

Charge is conserved: the sharing happens far faster than leakage removes anything.
Internal stack nodes start at zero volts, left there by the previous evaluate.
All capacitances are linear over the voltage range considered.

Q_{initial} = C_L\,V_{DD} - Before sharing, all the charge is on the precharged output node and the internal nodes hold none.
Q_{final} = (C_L+C_{int})\,V_{final} - After sharing, every connected node sits at the same voltage across the combined capacitance.
C_L V_{DD} = (C_L+C_{int})V_{final} - Charge is conserved, so the two expressions are equal.
V_{final} = V_{DD}\frac{C_L}{C_L+C_{int}} - Solve for the shared voltage. Note it depends on a ratio alone, not on any timing.
\Delta V = V_{DD}-V_{final} = V_{DD}\frac{C_{int}}{C_L+C_{int}} - The droop is the rest of the supply, and it grows with the internal capacitance the stack carries.
I_{keeper}\,t_{eval} > C_{int}V_{final} - For the keeper to restore the node within the evaluate window it must supply at least the charge that moved.

The droop is set by a capacitance ratio, so it is a structural property of the stack rather than something that can be timed around. Either the internal nodes are precharged too, or the keeper must be strong enough to replace the shared charge inside the evaluate window.

Charge sharing: V_{final} = V_{DD}\frac{C_L}{C_L+C_{int}} - Charge conservation between the output and the internal stack nodes.
Droop: \Delta V = V_{DD}\frac{C_{int}}{C_L+C_{int}} - Depends only on the capacitance ratio - not on how fast anything switched.
Keeper requirement: I_{keeper} > I_{leak,max} - At the highest operating temperature, which is where leakage is worst.
Contention limit: I_{keeper} \ll I_{pulldown} - The other side of the trade. The keeper must lose the fight during a real evaluate.
Keeper ratio: K = \frac{(W/L)_{keeper}}{(W/L)_{pulldown}} - Typically a few percent. The window narrows as leakage rises with each node.

A four-high stack with 3 fF on each of three internal nodes and 15 fF on the output, precharged to 1 V. If a partial pattern connects the output to all three internal nodes, the final voltage is 1 x 15/(15+9) = 0.625 V. That is a 375 mV droop with no path to ground at any point, and it is well past the noise margin of the receiving inverter. Precharging the internal nodes as well as the output removes the problem entirely, at the cost of one extra PMOS per internal node.

Charge sharing pulls a dynamic node down without any connection to ground. Where did the charge go?

Onto the internal capacitances of the pull-down stack. Those nodes were left discharged by the previous cycle, and a partial input pattern connects them to the output without completing a path to ground. Charge then redistributes between the output capacitance and the internal ones until they all reach a common voltage. No charge left the circuit - it simply spread over a larger total capacitance, so the voltage fell.

4. Why dynamic logic faded, and what survived

Dynamic logic was how the critical paths of high-frequency processors were built through the 1990s and early 2000s - wide comparators, address decoders, carry chains, register file decoders. The speed argument was real and the parts that used it were genuinely faster. It is now largely absent from new digital designs, and understanding why is more useful than the circuit itself, because the reasons are the same forces that shape every other modern design decision.

Leakage did most of the damage. A dynamic node holds its value as stored charge, and every process generation made charge harder to keep - subthreshold leakage rose as thresholds fell, gate leakage rose as oxides thinned, and both roughly doubled per ten degrees of temperature. The keeper that answers this must grow to match, but a bigger keeper fights the evaluate path harder, so the window between holding reliably at high temperature and evaluating correctly at low temperature narrowed with each node until it became difficult to close across the full corner space.

The rest was engineering cost. Dynamic gates need a clock at every gate, which raises clock power and clock-distribution complexity in a domain where the clock network was already a leading power consumer. The monotonicity rule cannot be checked by ordinary logic equivalence tools and needs specific structural verification. Noise margins are poor because a floating node has no restoring drive, so coupling from neighbouring wires matters far more. And static CMOS improved throughout: better libraries, better synthesis, and multiple threshold voltages gave much of the speed without any of the fragility. What survived is the reasoning - charge sharing, keepers, retention time and monotonicity all still appear wherever a node is left floating, which includes SRAM bitlines, sense amplifiers and low-swing interconnect.

First-order relation

\text{keeper window: } I_{leak}(T_{max}) < I_{keeper} \ll I_{pd}(T_{min})

Derivation: Show how the keeper design window narrows with each process generation.

The keeper must exceed worst-case leakage at maximum temperature to hold the node.
It must remain far below pull-down current at minimum temperature to avoid contention.
Both currents scale with process, but leakage scales faster than drive.

I_{keeper} > I_{leak}(T_{max}) - The lower bound: below this the node cannot be held against leakage in the hottest condition.
I_{keeper} < \epsilon\,I_{pd}(T_{min}) - The upper bound: the keeper must lose decisively during a real evaluate, with epsilon a small fraction.
\text{window} = \frac{\epsilon\,I_{pd}(T_{min})}{I_{leak}(T_{max})} - The ratio of the two bounds is how much design freedom is available.
I_{leak}\propto e^{-V_T/nkT} \Rightarrow I_{leak}\ \text{rises steeply as } V_T\ \text{falls} - Each generation lowered threshold voltage to keep speed at a lower supply, and leakage is exponential in threshold.
I_{pd}\ \text{rises sub-linearly, as velocity saturation caps drive} - Drive current stopped scaling with each node once carriers reached saturation velocity.
\frac{d}{d\text{node}}\left(\text{window}\right) < 0 - The numerator grows slowly while the denominator grows exponentially, so the window shrinks with every generation.

The window between a keeper that holds and a keeper that contends closes as leakage rises faster than drive. Beyond some point no keeper size satisfies both bounds across the full temperature and process corner space, and the family stops being usable regardless of its speed advantage.

Design window: I_{leak}(T_{max}) < I_{keeper} \ll I_{pd}(T_{min}) - Both bounds move the wrong way with scaling, which is what closed the window.
Clock power: P_{clk} = C_{clk}V_{DD}^{2}f - Every dynamic gate adds a clocked node, with an activity factor of one.
Activity factor: \alpha_{dyn} = 1 - A dynamic node switches every cycle regardless of data - static gates only switch when data changes.
Noise margin: NM_{H,dyn} \approx V_{DD}-V_{Tn} - No restoring drive on a floating node, so coupling and charge sharing eat directly into it.

Compare activity. A static gate with a typical data activity factor of 0.1 switches its output once every ten cycles. Its dynamic equivalent precharges and evaluates every single cycle, so its own node has an activity factor of 1 - ten times the switching energy on that node before counting the clock load on the precharge and evaluate devices. Dynamic logic buys delay with power, and it does so on every cycle whether or not the data changed.

If dynamic logic is still faster than static CMOS for wide functions, why did designs stop using it?

Because speed stopped being the binding constraint and the costs grew. Leakage made the keeper window narrow enough to be hard to close across all corners, the mandatory clock at every gate added power in a domain already dominated by clock distribution, monotonicity needed verification that standard equivalence checking does not do, and the floating node's poor noise margin got worse as wires coupled more tightly. Meanwhile static CMOS improved through better libraries and multiple threshold voltages, recovering much of the speed without the fragility.

Dynamic CMOS & Domino

1. Precharge and evaluate: computing with stored charge

Derivation: Find the minimum clock frequency a dynamic node can tolerate before leakage corrupts it.

A dynamic gate has no pull-up network, yet its output goes high. What drives it there, and what holds it there?

2. Domino: the cascading problem and its fix

Derivation: Show how much charge a non-monotonic input steals, and why it is unrecoverable.

Why does a footless domino gate work at all, given that its pull-down network has a direct path to ground with no evaluate transistor?

3. Charge sharing and the keeper

Derivation: Derive the shared voltage and the keeper size needed to survive it.

Charge sharing pulls a dynamic node down without any connection to ground. Where did the charge go?

4. Why dynamic logic faded, and what survived

Derivation: Show how the keeper design window narrows with each process generation.

If dynamic logic is still faster than static CMOS for wide functions, why did designs stop using it?

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