MICRO & NANO

How a wafer becomes a functioning device

A complete sand-to-transistor course with 52 lessons, a 17-step animated process flow, process equations, checkpoints, and cleanroom practice.

Reviewed 2026-08-225,570 wordsMicroelectronics students and engineers learning how unit processes integrate into a CMOS manufacturing flow.

Follow one device through the factory

The course begins with quartz purification, single-crystal growth, wafer preparation, and cleaning. It then follows a transistor cross-section through oxidation, lithography, etching, gate formation, self-aligned implantation, annealing, dielectric deposition, contact formation, metallization, passivation, and test. Each visible layer is connected to the operation that created it.

Understand each unit process physically

Oxidation changes silicon into dielectric through reaction and diffusion. Lithography transfers a temporary resist pattern with finite resolution and focus. Etching converts that pattern into material geometry. Implantation adds dopants while damaging the lattice, and annealing repairs damage while redistributing and activating dopants. Deposition and CMP build controlled films and restore planarity.

Calculate within model limits

Interactive labs expose ISO particle limits, Deal-Grove oxidation, Rayleigh resolution and depth of focus, etch selectivity and anisotropy, implant range, film growth, sheet resistance, CMP time, and yield. Every result is labeled as a model or educational approximation where appropriate. Learners check units, monotonic trends, boundary cases, and whether the model fits the process regime.

Integrate safety and manufacturability

Cleanroom protocol, chemical hazards, contamination control, metrology, thermal budget, overlay, aspect ratio, contact resistance, and defect density affect whether a theoretical device can be manufactured. Checkpoints require explaining both the desired mechanism and the process failure that a control prevents.

What you will be able to do

Sequence wafer, film, patterning, doping, interconnect, and test operations
Calculate cleanroom, oxidation, lithography, implant, deposition, and yield quantities
Explain why process order and thermal budget matter
Identify contamination, damage, geometry, and integration failure modes

The physics

First learn the repeating pattern: prepare a surface, add or modify a layer, define a pattern, transfer it, inspect it, then repeat with process control.

Semiconductor fabrication is an integration problem. A good oxidation, deposition, lithography, etch, or implant step can still fail if it damages the next interface or exceeds the thermal budget of an earlier layer.

Fabrication is a sequence of unit processes — cleaning, oxidation, deposition, lithography, etch, implantation, metallisation, CMP, packaging — whose results accumulate on the same wafer. Every earlier layer constrains the thermal budget, chemistry and topography of later steps.

Thermal oxidation of silicon follows the Deal–Grove model: at short times the film grows linearly (rate limited by the surface reaction), at long times parabolically (rate limited by oxidant diffusion through the existing oxide).

Photolithography transfers a mask pattern onto the wafer. The printable critical dimension (CD) is set by the wavelength λ, the numerical aperture NA and a process factor k₁; immersion and shorter wavelengths (DUV, EUV) shrink CD.

Etching must transfer the resist pattern into the film with control of anisotropy and selectivity. Wet etches are isotropic; plasma/RIE etches can be anisotropic because ions bombard the surface directionally.

Doping by diffusion follows Fick's law with a diffusion depth that grows as √(Dt); ion implantation places dopants with a depth profile controlled by energy and dose, then anneal activates them and repairs damage.

CMP planarises the surface by combining chemical dissolution with mechanical abrasion; removal rate depends on pressure, velocity and the slurry chemistry, and must stop at the correct thickness (end-point detection).

Process control measures thickness, CD, uniformity, particles, overlay, defect density and electrical yield at checkpoints, because a defect buried early can ruin the whole stack.

Formulas and where they apply

Deal–Grove oxidation: x² + A·x = B·(t + τ)

x: Oxide thickness
A: Linear-rate coefficient (2D/k)
B: Parabolic-rate constant
t: Oxidation time
τ: Offset time from initial oxide

Short time ⇒ x ≈ (B/A)t (reaction limited); long time ⇒ x² ≈ Bt (diffusion limited).

Lithography resolution: CD = k₁·λ / NA

CD: Critical dimension (minimum feature)
k₁: Process-dependent resolution factor (≈0.25–0.7)
λ: Exposure wavelength
NA: Numerical aperture of projection optics

EUV uses λ = 13.5 nm; immersion lithography increases effective NA above 1.

Etch anisotropy and selectivity: A_f = 1 − R_lat/R_vert · S = R_target/R_other

A_f: Anisotropy factor (1 = perfectly vertical)
R_lat: Lateral etch rate
R_vert: Vertical etch rate
S: Selectivity to the underlying layer

A_f = 1 means no undercut (ideal anisotropic); S >> 1 protects the stop layer.

Diffusion depth (anneal): x_j ≈ 2·√(D·t)

x_j: Junction/diffusion depth
D: Diffusivity (temperature dependent)
t: Time at temperature

D grows exponentially with temperature, so the thermal budget (temperature × time) controls the profile.

Sheet resistance of a layer: R_s = ρ / t

R_s: Sheet resistance
ρ: Resistivity of the layer
t: Layer thickness

R_s is independent of the square size — that is why the unit is 'ohms per square'.

What the measurement shows

Every process claim should be connected to a measurable result such as thickness, critical dimension, uniformity, resistivity, particles, overlay, defect density, or electrical yield.

Workflow

Follow the process flow from substrate to finished transistor.
For each step, write the input layer, intended change, and inspection method.
Study one defect mode and its root cause.
Connect the process result to a device parameter.

Procedure

List the process flow in order and record the start material (orientation, resistivity, particle spec).
For each unit process, write the intended change (grow, deposit, pattern, etch, dope, planarise) and its key metrology.
Identify the thermal budget: which already-formed layers must not be disturbed by later anneals.
Choose the critical parameter to control (CD, oxide thickness, junction depth, overlay) and its control limits.
Trace one defect mode back to its root cause and state which inspection would catch it.
Connect the final process result to the device parameters (threshold voltage, leakage, mobility, yield).

Reading the result

A measured thickness only means the intended one if the model (Deal–Grove, deposition calibration) was valid for the recipe.
Small CD errors are amplified by 1/L²-type device physics, so metrology precision matters more than it looks.
A defect found late is usually evidence of a process-control gap, not a random event.

Where it is used

Tracing a full CMOS flow from sand to packaged transistor for interviews and design reviews.
Diagnosing process excursions (oxide thickness, CD, doping) from metrology and electrical test data.
Choosing between wet and plasma etch, or between diffusion and implantation, for a given device requirement.

Common mistakes

Ignoring thermal budget: a high-temperature step after a shallow junction destroys it.
Assuming wet and plasma etches have the same anisotropy and selectivity.
Reporting a single wafer measurement as the process capability without uniformity data.

Limits of this method

Real fabs use qualified recipes, contamination control, safety systems, metrology, and statistical process control. An educational cross-section is not an operating procedure.

Silicon Wafer Manufacturing

Follow silicon from quartz ore to a polished wafer ready for its first oxidation.

From quartz to metallurgical silicon

Each purification stage removes a specific class of impurities; energy and chemistry set the achievable floor.

SiO₂ + 2C → Si + 2CO: At arc-furnace temperatures carbon strips oxygen from silica, leaving roughly 98–99% pure silicon.

quartz
carbothermic reduction
metallurgical grade
impurity budget

Polysilicon purification

Convert silicon into a volatile compound, distil that compound, then decompose it back into solid silicon.

Si + 3HCl → SiHCl₃ + H₂, then SiHCl₃ + H₂ → Si + 3HCl: Silicon becomes a volatile chlorosilane that can be distilled, then re-deposits as high-purity polycrystalline rods.

trichlorosilane
distillation
Siemens reactor
electronic grade

Czochralski crystal growth

The solid-liquid interface copies the seed's lattice; segregation decides which impurities stay in the melt.

C_solid = k · C_melt: The segregation coefficient relates dopant in the solidifying crystal to dopant remaining in the melt.

seed crystal
pull rate
segregation coefficient
oxygen incorporation

Wafering: slice, lap, polish

Each mechanical step removes the damage layer left by the previous step; polishing ends with a mirror surface.

wafers ≈ ingot length / (wafer thickness + kerf): Saw kerf turns part of every ingot into slurry, so thinner wafers and narrower kerf raise material yield.

wire saw
kerf loss
lapping
chemical-mechanical polish

Cleanroom Technology

Understand why particle control is a first-class engineering system, not housekeeping.

Why particles kill yield

A particle comparable to a feature size creates a fatal defect; yield falls exponentially with die area.

Y ≈ exp(−A · D₀): Poisson yield: larger die area and higher defect density both push the probability of a fatal defect upward.

critical dimension
defect density
killer particle
yield

ISO 14644-1 classification

Each ISO class is a formula, not a vibe: tenfold per class, size-dependent through a power law.

C_N(D) = 10^N · (0.1/D)^2.08: The maximum particle concentration per m³ at diameter D follows the ISO class N formula.

ISO 14644-1
particle limit
FED-STD-209E
class number

Airflow, filtration and pressure cascades

Cleanrooms dilute or sweep away contamination faster than people and tools generate it.

steady count = generation rate / filtered airflow: Steady-state particle concentration is set by the balance of generation and filtered removal.

HEPA
ULPA
laminar flow
air changes per hour

People, gowning and protocols

Every motion sheds particles; protocols reduce generation and garments trap what is shed.

shedding ∝ motion × exposed skin: Particle generation rises with activity and uncovered surfaces, which gowning and discipline suppress.

bunny suit
gowning sequence
behaviour rules
particle shedding

Wafer Cleaning and RCA

Learn why every process step starts with a surface free of particles, organics and metals.

Four contamination classes

Diagnosis drives chemistry: each contaminant class binds differently, so each needs a different attack.

clean = f(contaminant class, chemistry, energy, time): Cleaning effectiveness is a matched pair of contaminant type and removal mechanism.

particles
organic residue
metallic contamination
native oxide

RCA SC-1 and SC-2

SC-1 lifts particles with peroxide chemistry; SC-2 keeps metals dissolved and off the surface.

SC-1: NH₄OH:H₂O₂:H₂O ≈ 1:1:5 · SC-2: HCl:H₂O₂:H₂O ≈ 1:1:6: Dilute chemistries at 75–80 °C remove particles and metals without attacking silicon aggressively.

SC-1 APM
SC-2 HPM
peroxide chemistry
zeta potential

Piranha and HF-last

Piranha oxidises organics aggressively; HF strips native oxide so growth starts on hydrogen-terminated silicon.

SiO₂ + 6HF → H₂SiF₆ + 2H₂O: HF dissolves silicon dioxide, removing native oxide and leaving a hydrophobic, passivated surface.

piranha
HF dip
native oxide
H-terminated surface

Verifying a clean surface

A clean is only real when measured: particles, metals and wetting each need their own evidence.

evidence = particles + metals + wetting + records: Cleaning verification combines optical inspection, chemical analysis and surface-energy checks.

contact angle
surface inspection
trace metal analysis
wafer history

Thermal Oxidation

Grow the gate dielectric that makes the MOSFET possible.

Why silicon dioxide

Silicon's superpower is that it grows its own excellent insulator; few semiconductors can do that.

Si + O₂ → SiO₂: Oxidation consumes silicon to form a dense, stable insulator with an electrically quiet interface.

gate dielectric
interface states
band offset
thermal stability

The Deal–Grove model

Early growth is reaction-limited and linear; later growth is diffusion-limited and parabolic.

x² + A·x = B·(t + τ): Oxide thickness x solves a quadratic combining interface reaction and oxidant diffusion through existing oxide.

linear regime
parabolic regime
rate constants
activation energy

Dry versus wet oxidation

Water diffuses faster through silica than oxygen, so wet oxidation is faster but less dense.

B_wet ≫ B_dry at equal temperature: The parabolic rate constant is much larger for wet oxidation, giving faster thick growth.

dry O₂
wet ambient
growth rate
oxide quality

Oxidation side effects

Oxide grows into the silicon, not just on top of it, and it redistributes dopants as it advances.

x_Si ≈ 0.44 · x_oxide: Growing an oxide consumes about 44% of its thickness in silicon.

silicon consumption
segregation
bird's beak
stress

Photolithography

Define patterns with light: the resolution engine of the whole fab.

Lithography as pattern transfer

Lithography writes a temporary mask in resist; etching or implantation makes it permanent.

CD_final = CD_mask + exposure bias + etch bias: The printed dimension accumulates contributions from mask, optics and transfer steps.

critical dimension
resist image
pattern transfer
overlay

Resolution: Rayleigh criterion

Resolution is a three-knob instrument: shorter wavelength, larger NA, smaller k₁.

CD = k₁ · λ / NA: The minimum printable feature scales with wavelength and process difficulty, and inversely with NA.

wavelength
numerical aperture
k₁ factor
resolution

Depth of focus and process window

Resolution and depth of focus fight each other: pushing NA improves one and punishes the other.

DOF = ± k₂ · λ / NA²: Allowable focus error scales with wavelength but with the inverse square of NA.

depth of focus
process window
focal budget
topography

Exposure systems: stepper to EUV

Every generation trades mask damage, field size, resolution and cost differently.

printed uniformity ∝ optics + stage + control: Printed uniformity is a system property of optics, wafer stage and control loops.

stepper
scanner
reduction optics
EUV

Photoresists, Masks and Alignment

Master the materials and alignment discipline behind every printed layer.

Positive versus negative resist

Positive resist exposes to dissolve; negative resist exposes to crosslink and stay.

γ = [log(E₂/E₁)]⁻¹: Resist contrast measures how sharply solubility switches with dose; higher contrast prints steeper walls.

positive resist
negative resist
contrast
swelling

Photomasks and reticles

The mask is the master copy: its defects print, so it is protected and inspected like a product.

wafer CD = reticle CD / reduction ratio: A 4× reticle relaxes mask CD tolerances because the image is demagnified onto the wafer.

chrome on glass
pellicle
reticle reduction
mask inspection

Alignment and overlay

Overlay is a budget spent by every tool and step; run out and devices disconnect.

σ_total² = σ_tool² + σ_process² + σ_mark²: Overlay error accumulates as the root-sum-square of tool, process and mark contributions.

alignment marks
overlay budget
registration
interlevel error

The resist process sequence

Each bake and step sets resist chemistry state; skipping one shifts dose-to-size.

CD = f(dose, focus, PEB, develop): Printed size is a joint function of exposure dose, focus and every thermal and wet step around it.

spin coat
soft bake
post-exposure bake
develop

Wet and Dry Etching

Transfer resist patterns into real materials with control over shape and selectivity.

Wet etching

Wet etch attacks all directions equally, so features shrink under the mask as they deepen.

undercut ≈ etch depth (isotropic limit): In a fully isotropic etch, lateral erosion under the mask grows with depth.

isotropic
undercut
selectivity
batch processing

Plasma and reactive-ion etching

Chemistry does the etching; ions aim it, carving vertically while sidewalls stay protected.

rate = chemical term × ion-assisted term: Dry etch rate couples neutral chemistry with directional ion energy.

plasma
ion bombardment
sidewall passivation
RIE

Anisotropy and selectivity metrics

Two ratios decide success: vertical versus lateral etch, and film versus mask etch.

A_f = 1 − (lateral rate / vertical rate): Anisotropy of 1 means perfectly vertical; 0 means fully isotropic.

anisotropy
selectivity
etch bias
endpoint

Etch defects and non-uniformities

Etch rate depends on local pattern density; dense and open areas etch differently.

rate = f(local pattern density, aspect ratio): Local consumption of etchants and ion transport make rate vary with pattern density.

loading
microloading
residues
aspect-ratio-dependent etch

Diffusion and Ion Implantation

Place dopant atoms exactly where the device needs them.

Fick's laws of diffusion

Dopants walk downhill in concentration; temperature sets how fast they walk.

∂C/∂t = D · ∂²C/∂x²: Concentration changes where the curvature of the profile drives net diffusion.

Fick's first law
Fick's second law
diffusivity
activation energy

Predeposition and drive-in

Predeposition loads dopant in; drive-in pushes it deeper while the total dose stays fixed.

Q = ∫C dx conserved during drive-in: During drive-in the total dopant per area is conserved while the profile broadens.

predeposition
drive-in
erfc profile
gaussian profile

Ion implantation: energy, dose and range

Ions slow by collisions; heavier ions stop sooner, higher energy goes deeper.

C(x) ≈ Gaussian(R_p, ΔR_p): The implanted profile is approximately gaussian centred at the projected range with straggle as its width.

projected range
straggle
dose
energy

Implant damage and annealing

Implantation wrecks the lattice; annealing repairs it and moves dopants onto active sites.

active dose ≤ implanted dose: Only dopants on substitutional sites contribute carriers, so activation is never complete.

amorphisation
channeling
activation
rapid thermal anneal

PVD, CVD and ALD

Add films with controlled thickness, stress and coverage.

What a film must deliver

A film is a spec sheet, not just a layer: each property couples to later process steps.

uniformity = (max − min) / (max + min): Thickness uniformity quantifies spread across the wafer.

uniformity
stress
step coverage
purity

PVD: evaporation and sputtering

PVD throws atoms at the wafer; line-of-sight travel limits step coverage.

rate ∝ power density / target area: Deposition rate follows the energy delivered to the source material.

evaporation
sputtering
line of sight
target

CVD: APCVD, LPCVD, PECVD

CVD grows films by surface chemistry; pressure and plasma trade temperature against quality.

rate ∝ exp(−Eₐ/kT) (reaction-limited): In the reaction-limited regime, growth rate rises exponentially with temperature.

APCVD
LPCVD
PECVD
precursor chemistry

ALD: self-limiting cycles

Each pulse saturates the surface, so one cycle adds one fixed increment regardless of time.

thickness = GPC × cycles: Growth per cycle times cycle count sets thickness, giving exceptional control.

self-limiting
cycle
conformality
nucleation

Metallization

Wire the devices together with metal that survives current, heat and time.

Interconnect requirements

Interconnects are wires with reliability specs: resistance, current density and lifetime.

RC delay ∝ ρ_wire · C_line: Interconnect delay scales with wire resistivity and line capacitance.

resistivity
electromigration
adhesion
stress voiding

Aluminium and tungsten plugs

Tungsten fills vertical holes; aluminium runs horizontal wires; each job fits a material.

plug R = ρL/A: Contact plug resistance follows resistivity, length and cross-section.

tungsten plug
CVD tungsten
Al sputter
contact fill

Copper damascene

Copper cannot be etched easily, so the industry etches the dielectric and fills it instead.

fill = barrier + seed + plate − CMP overburden: Damascene builds metal by overfilling then polishing back to the dielectric surface.

dual damascene
barrier layer
electroplating
CMP

Contacts, silicides and barriers

Every metal-silicon interface is engineered: contact resistance and diffusion both matter.

ρ_c = contact resistivity (Ω·cm²): Contact resistivity quantifies the interface itself, independent of contact area.

ohmic contact
silicide
Schottky
Ti/TiN barrier

Chemical-Mechanical Planarization

Flatten the wafer so the next lithography layer stays in focus.

Why planarization

Each metal layer adds hills; without flattening, later layers print out of focus.

usable layers ∝ DOF / topography per layer: The number of stackable layers is limited by how much topography focus budgets tolerate.

topography
depth of focus
multilevel interconnect
planarization

CMP mechanism and Preston's equation

Chemistry softens the surface; mechanics abrade it away; both must stay balanced.

RR = K_p · P · V: Removal rate equals Preston coefficient times down pressure times relative velocity.

slurry
pad
Preston coefficient
removal rate

Dishing, erosion and scratches

Polish rate depends on material and pattern density; non-uniformity carves the surface.

dishing ∝ metal width × rate mismatch: Wide metal features dish more because they polish faster than surrounding dielectric.

dishing
erosion
scratch
pattern density

Endpoint and metrology

Stop at the right interface using in-situ signals, then verify with independent metrology.

overpolish = safety margin × non-uniformity: Overpolish budget compensates for thickness and rate variation across the wafer.

endpoint
optical detection
thickness map
defect scan

Packaging and Testing

Turn fragile dice into reliable products and prove they work.

Back-end: dice, attach, bond

Back-end converts a tested die into a handled, connected, cooled product.

assembly = mechanical + electrical + thermal paths: A package must simultaneously hold, connect and cool the die.

dicing
die attach
wire bond
flip chip

Package functions and types

Every package is a compromise among pins, size, power and cost.

θ_JA = θ_JC + θ_CS + θ_SA: Junction-to-ambient thermal resistance is a series stack from die to air.

protection
thermal path
leadframe
BGA

Test levels: probe, final, burn-in

Each test level catches a different defect population at the cheapest possible point.

cost of escape ∝ stage at which defect is found: The later a defect is caught, the more it costs; test early, test cheaply.

wafer probe
final test
burn-in
test coverage

Yield economics

Cost per good die divides total cost by surviving dice; yield multiplies everything.

DPW ≈ πd²/(4A) − πd/√(2A): Die per wafer approximates usable dice from wafer area minus edge losses.

die per wafer
Poisson yield
cost per die
defect density

Complete CMOS Flow

Assemble every unit process into the MOSFET: from sand to silicon transistor.

Process integration philosophy

Integration is sequencing under constraints: heat, alignment and contamination budgets.

flow = Σ steps subject to budgets: A process flow is a sequence that respects every accumulated thermal, alignment and contamination budget.

thermal budget
sequencing
cross-contamination
design rules

The n-well CMOS flow

CMOS builds n and p devices side by side; wells, isolation and gates interleave deliberately.

CMOS = NMOS + PMOS + isolation + wiring: The CMOS flow integrates complementary devices with shared isolation and interconnect.

n-well
isolation
gate stack
interconnect

From sand to silicon transistor

Every transistor is a stack of decisions: purification, crystal, pattern, dope, wire, test.

transistor = wafer + oxidation + litho + etch + doping + films + metal: The device is the cumulative result of every unit process applied in order.

end-to-end flow
cross-section
layer stack
process history

Technology nodes and scaling

Node names are marketing labels; real scaling is density, power and interconnect engineering.

density ∝ 1 / (pitch_x · pitch_y): Transistor density follows the inverse of patterning pitch in both directions.

technology node
Dennard scaling
FinFET
interconnect pitch