Electronics Technology 1

Electronic product development

Begin with an observable requirement: a sensor must resolve a specified change, operate over a temperature range and survive an installation environment. Turn each requirement into a verification method before selecting components. A prototype explores uncertain mechanisms; a qualified design has documented evidence against its requirements.

The lifecycle moves from concept through architecture, schematic, layout, assembly, test and release. Design for manufacture (DFM) checks what a fabrication process can reliably produce. Design for assembly (DFA) checks access, placement, polarity, soldering and inspection. A design can pass electrical simulation yet fail because a connector cannot be inserted or a joint cannot be inspected.

Build the physical picture

An electronic product is a coupled physical system. Accuracy can be limited by the sensor, analogue front end, voltage reference, firmware arithmetic or mechanics. Start with the required behaviour and allocate an error, power and timing budget across these contributors. This prevents optimizing a component that does not dominate the result.

A requirement must specify its conditions: “works at 85 °C” is incomplete without supply, duty cycle, airflow and acceptable performance. Verification tests a stated requirement; validation asks whether meeting those requirements solves the actual user problem.

From mechanism to a usable model

A demonstrator is designed to learn quickly; a manufacturable design must also tolerate component spread, assembly variation, service and misuse within stated limits. Record uncertain assumptions separately from decisions already supported by evidence. Review failure severity and detectability early, rather than treating test as a final pass/fail ceremony.

Design margin = demonstrated capability − required capability

Model assumptions: Define units and a favourable direction; for latency, lower is better, so margin is limit minus measured latency.

Allocate a measurement error budget

Identify independent and correlated error sources.

For a guaranteed worst-case bound, add magnitudes; for justified independent random standard uncertainties, combine by root-sum-square.

Compare with the required bound and reserve margin for temperature and manufacturing spread.

Mistake to avoid: RSS is not a safe replacement for worst-case addition when errors are systematic or correlated.

Worked problem: A display must respond within 100 ms. The measured 95th percentile is 72 ms and the maximum observed is 118 ms. Has the requirement passed?

The answer depends on the requirement’s quantifier. A guaranteed 100 ms bound fails the observed test. A 95th-percentile requirement has 28 ms measured margin, but sample size and confidence still matter. Record the 118 ms event and investigate it.

Self-test: Why should test planning precede implementation?

It prevents vague success claims and exposes missing sensors, access points and acceptance criteria while changes are inexpensive.

Two independent random errors have standard deviations 2 mV and 3 mV. What is their combined standard uncertainty?

√(2²+3²)=3.61 mV. A worst-case sum of magnitude limits would instead be 5 mV; the statistical assumptions must be stated.

PCB structure and materials

A PCB consists of copper conductors separated by dielectric layers. FR-4 describes a family of glass-reinforced flame-retardant epoxy laminates, not one universal dielectric constant. Copper thickness and trace geometry determine resistance; dielectric permittivity sets capacitance and propagation, while loss tangent contributes dielectric loss.

Glass-transition temperature Tg marks a change in polymer behaviour rather than a safe operating temperature. Thermal expansion, particularly through the thickness, loads plated holes and joints. Surface finishes protect exposed copper and support joining; choose them with storage, planarity, corrosion and assembly requirements.

Build the physical picture

A multilayer board is an electrical and mechanical stack, not only a drawing of traces. Signal layers, reference planes, dielectric thicknesses and copper weights jointly determine routing capacity, impedance, return paths and warpage. A reference plane close to a signal gives a smaller field region and usually reduces loop inductance.

Material selection requires a property at the relevant conditions. Dielectric constant varies with frequency and test method; loss tangent describes dielectric energy loss. Copper roughness increases high-frequency conductor loss. Water uptake and thermal expansion can change reliability as well as electrical behaviour.

From mechanism to a usable model

Compare Tg, decomposition behaviour and expansion rather than equating a high Tg with unlimited process tolerance. Glass and polymer have different properties, creating local anisotropy and weave effects. A stackup should be agreed with the fabricator before a tightly controlled layout is finalized; nominal CAD thickness alone does not establish the fabricated impedance.

C ≈ ε₀εᵣ A/d; ΔL = αLΔT

Model assumptions: Parallel-plate capacitance neglects fringing; use laminate properties at the relevant frequency and temperature.

Relate geometry to resistance and capacitance

Use R=ρL/(wt) for a uniform DC conductor.

Use C≈εA/d only where the parallel-plate approximation is credible.

Predict directions: wider/thicker copper reduces DC resistance; smaller dielectric separation increases capacitance.

Mistake to avoid: Copper width alone does not define transmission-line impedance; reference geometry and dielectric properties matter.

Worked problem: Estimate capacitance between 1 cm² copper areas separated by 0.2 mm dielectric with εᵣ=4.

A=10⁻⁴ m² and d=2×10⁻⁴ m. C=8.854×10⁻¹²×4×A/d=17.7 pF. Fringing and local weave can change the real value.

Self-test: Why is “FR-4 has εᵣ=4” insufficient for RF design?

It omits material grade, frequency, test method, anisotropy and manufacturing variation.

What happens to ideal plane capacitance when separation halves at fixed area and dielectric?

It doubles. The same change alters field distribution and routing impedance, so it is not merely an isolated capacitor change.

PCB manufacturing

Fabrication transfers a digital conductor pattern into physical layers. In a representative subtractive process, image and etch inner copper, align and laminate layers, drill holes, prepare their walls, deposit conductive seed and plate copper, then pattern outer conductors and apply solder mask and finish. The exact order changes with the stack and process.

Registration error, etch undercut, hole aspect ratio and plating distribution limit achievable geometry. A plated via must form a continuous conductor along the wall; it is not a solid ideal copper cylinder. Fabrication coupons and cross-sections verify properties that a schematic cannot show.

Build the physical picture

PCB fabrication transfers a patterned design into a laminate and adds vertical connectivity. Inner layers are imaged and etched, bonded into a stack, then holes are created, cleaned and metallized according to the chosen process. Outer-layer imaging/plating, solder mask, surface finish and electrical inspection complete the assembly substrate. Sequence details vary with subtractive, additive and HDI processes.

A plated hole must connect its intended pads despite drilling and layer-registration error. Annular ring is the copper left around the hole; insufficient ring risks breakout. Hole-wall cleaning and plating quality matter because a visually correct pad can hide an unreliable barrel.

From mechanism to a usable model

Manufacturing limits are tolerances, not just minimum feature numbers. Etch changes width; plating changes holes; registration shifts layers. Ask for the actual finished-hole and copper specification. Electrical bare-board testing detects opens and shorts but does not by itself qualify fatigue life, dielectric integrity or every latent process defect.

Hole aspect ratio = board thickness / drilled diameter

Model assumptions: Conventional drilled through-hole estimate; microvia qualification uses different process constraints.

Check an annular-ring allowance

Start with pad diameter and finished-hole diameter.

Compute nominal radial ring as half their difference.

Subtract worst-case radial misregistration and dimensional tolerances; compare with the fabricator’s requirement.

Mistake to avoid: A drill file diameter and a finished plated-hole diameter need not be identical.

Worked problem: A 1.6 mm board has 0.20 mm drilled holes. Find aspect ratio and explain its significance.

1.6/0.20=8:1. A deeper narrow hole is harder to plate uniformly. Ask the selected fabricator about its qualified process instead of assuming that 8:1 always passes.

Self-test: Why can an electrically connected via still have poor reliability?

Thin or defective barrel plating can crack under thermomechanical strain while initially passing continuity.

A 0.8 mm pad surrounds a 0.4 mm finished hole. Ignoring other tolerances, what ring remains after 0.08 mm radial offset?

Nominal ring is 0.2 mm; the narrow side retains 0.12 mm. Other tolerances can reduce it further.

PCB design workflow

Translate requirements into a schematic with explicit power, signal and connector interfaces. Assign verified footprints and choose a stackup with the manufacturer before routing. Placement fixes most current paths: keep switching loops compact, decoupling close, return paths continuous and sensitive nodes away from interference.

Electrical-rule checks find schematic inconsistencies; design-rule checks compare geometry with declared constraints. Neither proves correct pin mapping, signal integrity or assembly access. Release fabrication and assembly outputs together with revision, stackup, drill data, bill of materials and placement information.

Build the physical picture

The schematic expresses connectivity and intent; layout adds physical geometry. First place components according to functional groups and current paths: switching-power loops, decoupling loops, clock distribution and sensitive analogue regions. A short signal trace can still be poor if its return current must detour around a plane split.

Rules translate design constraints into checks: clearances, width, via dimensions, controlled impedance and differential-pair restrictions. Electrical-rule checking flags schematic issues, while design-rule checking flags configured layout constraints. Neither understands every application requirement or a wrongly configured rule.

From mechanism to a usable model

Before fabrication, review power-up states, unused pins, connector orientation, test access and assembly documentation. Provide a consistent release package including fabrication files, stackup, BOM, placement data and revision. A reviewer should be able to reconstruct which physical board corresponds to which schematic and firmware version.

Trace width and clearance constraints come from current, voltage, impedance and fabrication

Model assumptions: A CAD default is a geometry setting, not a physical requirement.

Review a critical routing path

Locate its outgoing and return currents, not only the coloured CAD trace.

Identify layer changes, discontinuities and nearby aggressors.

Check geometry and tolerance against the intended electrical function, then verify manufacturing outputs.

Mistake to avoid: A clean DRC report proves compliance with the configured rules, not overall engineering correctness.

Worked problem: DRC reports zero errors, but an IC footprint is mirrored. Why was the error missed?

DRC checks geometric rules and net relationships. A wrongly defined footprint can be internally consistent. Compare pin numbering and orientation against the package drawing and inspect an assembly view.

Self-test: What should be checked before ordering a board?

Footprints, polarity, connector mating, clearances, stackup, power paths, test access and consistent fabrication/assembly revisions.

Why can a signal crossing a split plane cause problems even if its trace is short?

Its high-frequency return current is forced to detour, increasing loop area and inductance and potentially creating common-mode radiation or coupling.

Electrical PCB behaviour

A trace dissipates energy through resistance and stores energy in its surrounding electric and magnetic fields. At low frequency it may be treated as a lumped connection. When propagation delay becomes significant relative to edge time, treat it as a transmission line. Signal return current follows the lowest impedance path, which at high frequency often lies near the trace on its reference plane.

A break in that plane forces a longer return loop, increasing inductance and coupling. Inductive voltage depends on current change, so a modest DC current can produce a large transient if switched quickly.

Build the physical picture

A trace behaves approximately as a lumped wire only when propagation delay is small relative to the relevant edge time. Digital rise time, rather than clock frequency alone, determines when distributed transmission-line effects matter. A slowly repeating signal with a fast edge can still reflect strongly.

Fields store energy through distributed capacitance and inductance. Characteristic impedance is the voltage/current ratio of a travelling wave, not the trace’s DC resistance. At a load discontinuity, part of that wave reflects; Γ=(ZL−Z0)/(ZL+Z0) describes the reflected-to-incident voltage ratio for the simple line model.

From mechanism to a usable model

Power distribution also has frequency-dependent impedance. Capacitor ESL and ESR, vias and planes determine where decoupling is effective. Place a local capacitor to minimize the actual current loop, including both connections. Excessively ideal capacitance-only reasoning hides resonances and inductive voltage steps.

R=ρL/(wt); V_L=L_ind·di/dt

Model assumptions: Uniform copper at constant temperature; L_ind is inductance, while L in the resistance expression is length.

Estimate whether a line needs distributed treatment

Estimate one-way delay from length and propagation velocity.

Compare the delay with edge time and the accuracy required; use a transmission-line model when it is not negligible.

Evaluate source/load impedances and predict reflection sign before selecting termination.

Mistake to avoid: A 50 Ω trace is not a 50 Ω DC resistor.

Worked problem: For copper ρ=1.68×10⁻⁸ Ωm, find R for a 50 mm × 0.5 mm × 35 µm trace.

Cross-section=0.0005×35×10⁻⁶=1.75×10⁻⁸ m². R=0.048 Ω. At 1 A, drop=48 mV and loss=48 mW; heating increases resistivity.

Self-test: Why is a ground-plane slot dangerous beneath a fast signal?

It interrupts the nearby return path, expands the loop and can change impedance and emissions.

For Z0=50 Ω and an open load, what is Γ? What about a 50 Ω load?

An ideal open has Γ→+1; a matched 50 Ω load has Γ=0. The source boundary determines subsequent reflections.

Thermal management

Electrical loss becomes heat that must move through the die, package, interfaces, board and surrounding air. Thermal resistance relates steady power to temperature rise; thermal capacitance explains why the rise takes time. A copper area or thermal via helps only when it connects to a useful downstream heat path.

Datasheet junction-to-ambient resistance is measured under specified board and airflow conditions. It is not a universal package constant. Build the actual thermal path, include interface resistance, calculate a first estimate and verify under the worst relevant load and ambient conditions.

Build the physical picture

Heat generation, storage and transport are distinct. Dissipated electrical power creates heat; thermal mass stores it; conduction, convection and radiation remove it. Thermal resistance describes a steady-state temperature difference per heat-flow rate, while thermal capacitance describes stored energy per temperature change.

The thermal path can include die, package, solder, copper spreading, board and ambient. A datasheet junction-to-ambient number belongs to a specified test setup. It is not a universal package property transferable unchanged to any PCB or airflow condition.

From mechanism to a usable model

For a single lumped path, Cth dT/dt=P−(T−Tamb)/Rth. The solution to a power step approaches Tamb+P Rth with time constant Rth Cth. Real assemblies need multiple paths or spatial models when hotspots, short pulses and spreading dominate. The simple model is valuable because it separates final temperature from heating speed.

Tⱼ=Tₐ+P Rθ; τ=Rθ Cθ

Model assumptions: Lumped linear model with constant power and one dominant time constant; excludes spatial hot spots.

Solve a thermal power step

Find the steady rise P Rth.

Calculate τ=Rth Cth, keeping K/W and J/K consistent.

Evaluate ΔT(t)=P Rth[1−exp(−t/τ)] and compare with component and material limits.

Mistake to avoid: Adding thermal mass delays heating but does not necessarily lower the final steady-state temperature.

Worked problem: A device dissipates 2 W with an effective 30 K/W path at 40 °C ambient. Find steady junction temperature.

Rise=2×30=60 K. Tⱼ=100 °C. Compare with the operating limit, include uncertainty, and measure a justified case-to-junction estimate or calibrated sensor.

Self-test: Why can two identical packages reach different temperatures?

Board copper, interface pressure, airflow, orientation, adjacent heat sources and workload alter the effective path.

For P=1 W, Rth=40 K/W and Cth=2 J/K, find the rise after 80 s.

τ=80 s; ΔT=40(1−e⁻¹)≈25.3 K. Final rise is 40 K, independently of Cth in this model.

Electronic components and packages

The package connects a small die to an assembly while protecting it and carrying heat and stress. Through-hole leads can support mechanical loads but consume area and introduce lead inductance. Surface-mount packages include gull-wing leads, leadless QFN and area-array BGA contacts. Each creates different inspection and rework constraints.

A MEMS package may need a controlled cavity or access to pressure or motion. Chip-on-board connects a bare die directly to a substrate and requires appropriate die attachment, bonding and protection. Choose packaging from electrical, thermal, mechanical and manufacturing requirements together.

Build the physical picture

A package provides mechanical protection, electrical connections and a thermal path. Leadframes, bond wires, solder bumps and substrates introduce parasitic resistance, inductance and capacitance. Package choice therefore affects switching noise, RF behaviour and heat removal, not merely board footprint.

QFN, BGA and leaded packages offer different density, inspectability and assembly constraints. An exposed thermal pad may require solder coverage, vias and stencil design consistent with the manufacturer’s recommendation. A ball array hides joints, so inspection and rework strategy must be considered before production.

From mechanism to a usable model

Component values also have operating dependence. A ceramic capacitor can lose significant effective capacitance under DC bias, depending on dielectric and construction. A resistor has tolerance and temperature coefficient; a connector has current and environmental limits. Read guaranteed ratings and curves rather than designing from the nominal label alone.

V_parasitic=L_lead·di/dt

Model assumptions: Inductance belongs to the complete current loop, not just an isolated labelled lead.

Trace a package limitation to a circuit effect

Identify an interconnect parasitic and the current or voltage waveform crossing it.

Use a first-order relation such as ΔV=L di/dt to estimate its consequence.

Compare package, PCB and probe contributions before attributing the observed waveform to the die.

Mistake to avoid: A pin-compatible replacement can still change parasitics, thermal performance or assembly requirements.

Worked problem: A package loop has 2 nH inductance and current changes at 0.1 A/ns. Estimate transient voltage.

0.1 A/ns=10⁸ A/s. V=2×10⁻⁹×10⁸=0.2 V. This is substantial for a low-voltage rail; reduce loop inductance and provide local charge.

Self-test: Why may BGA joints require X-ray inspection?

Their connections are hidden below the body, so ordinary optical inspection cannot directly assess all joints.

If an interconnect has 2 nH inductance and current changes at 0.1 A/ns, estimate the inductive voltage.

L di/dt=2×10⁻⁹×10⁸=0.2 V. The actual waveform also depends on the full loop and circuit impedances.

Soldering processes

Solder joins surfaces through wetting and metallurgical interaction. Oxide inhibits wetting, so surface preparation and flux chemistry matter. Paste contains alloy particles and flux; stencil apertures control deposited volume. During reflow, heat activates flux and melts the alloy, then controlled cooling forms the joint.

A profile includes ramp, soak where appropriate, time above liquidus and peak temperature. The allowable window comes from solder, components and board limits. Bridges can result from excess paste or poor spacing; tombstoning results from unequal forces during wetting. A shiny appearance alone does not prove a sound joint.

Build the physical picture

Soldering forms a metallurgical joint through wetting and interfacial reaction. Flux removes or disrupts oxides so molten solder can contact clean metal. The resulting intermetallic layer is necessary, but excessive growth or unsuitable interfaces can degrade reliability. A shiny external shape alone does not prove the internal joint is sound.

Reflow heats deposited paste and components through a controlled profile; wave and selective soldering suit other geometries. Ramp, soak, time above liquidus and peak must fit alloy, paste, component and board constraints. Uneven thermal response can cause defects even when the oven setpoint looks correct.

From mechanism to a usable model

Tombstoning results from unbalanced forces during melting, often involving unequal wetting or thermal timing. Voids, bridging and insufficient solder have different causes and corrective actions. Inspection should distinguish geometry defects from process evidence; changing temperature indiscriminately can trade one defect for another.

TAL = duration for which T(t) exceeds alloy liquidus

Model assumptions: Actual assembly temperature differs from oven settings; measure the relevant joints with a qualified profile.

Interpret a temperature profile

Measure at representative small, large and thermally connected components.

Compare actual joint temperatures with the approved process window.

Relate defects to wetting, paste volume, geometry and thermal imbalance before altering the recipe.

Mistake to avoid: The oven air temperature is not automatically the solder-joint temperature.

Worked problem: A joint crosses liquidus at 90 s and falls below it at 145 s. Compute TAL.

TAL=145−90=55 s. Acceptability requires the alloy and assembly process specification; 55 s is a measured parameter, not a universal pass condition.

Self-test: Why can a component stand on one end during reflow?

Asymmetric heating, pad design or paste creates unequal wetting forces before both joints stabilize.

Why can the two ends of a tiny resistor heat differently?

Different copper connections and local thermal mass produce unequal heat flow. One side may wet earlier, causing a force imbalance that lifts the component.

Bonding, adhesives and dispensing

Wire bonding forms small metallic connections through controlled force, energy and contact conditions. Die attach secures a die and may carry heat or current; it can use solder, sintered material or adhesive. Dispensing controls where and how much adhesive is placed, while curing develops its final properties.

Underfill fills the gap under a flip-chip and redistributes strain between bumps and substrate. Its benefits depend on modulus, expansion coefficient, adhesion and cure. Voids, contamination and incomplete cure can create thermal or mechanical failure even when initial electrical continuity is correct.

Build the physical picture

Wire bonding joins small conductive wires to die pads and package terminals using controlled force, energy and material deformation. Adhesive bonding instead transfers load through a polymeric or composite interface; conductive adhesives also provide electrical paths through fillers. Their mechanisms and qualification tests are different.

Surface condition, contamination and cure determine adhesion. A nominally strong adhesive can fail at a poorly prepared interface. Cure shrinkage and thermal expansion can stress a die or sensor, changing electrical output before a visible mechanical failure occurs.

From mechanism to a usable model

Dispensing involves rheology as well as nominal volume. Viscosity, filler settling, pot life, nozzle dimensions and pressure affect dot shape and consistency. Cure schedule changes network formation and final properties. The useful question is not “which glue is strongest?” but whether the joint meets conductivity, thermal, mechanical and environmental requirements.

Δε≈(α_substrate−α_die)ΔT

Model assumptions: A free-expansion mismatch estimate; actual joint stresses require geometry and mechanical properties.

Estimate mismatch strain

Identify the expansion coefficients of the bonded materials.

Calculate free differential strain Δε=(α1−α2)ΔT.

Use joint geometry and compliance to reason about stress; do not equate this strain directly with stress without a constitutive model.

Mistake to avoid: Adhesive bulk strength does not guarantee interface adhesion or fatigue life.

Worked problem: CTE mismatch is 12 ppm/K across an 80 K cycle. Estimate differential strain.

Δε=12×10⁻⁶×80=9.6×10⁻⁴, or 0.096%. Repetition can accumulate fatigue damage depending on constraints and material behaviour.

Self-test: Why does more adhesive not necessarily improve die attachment?

Excess changes bond-line thickness, stress, cure, contamination and thermal resistance; placement must follow a controlled process.

Two bonded materials differ in CTE by 15 ppm/K. What differential free strain arises over 100 K?

15×10⁻⁶×100=0.0015, or 0.15%. Constraint and adhesive compliance determine the resulting stress.

EMI and EMC

Electromagnetic interference needs a source, a coupling path and a susceptible receiver. Capacitive coupling follows changing voltage; inductive coupling follows changing current and shared loop flux. Common-impedance coupling occurs when circuits share a non-ideal return conductor. Radiated coupling depends on geometry, frequency and cables.

Control interference at its source, route the return close to the outgoing current, and select filtering or shielding for the path. EMC concerns both emissions and immunity. A filter only works with a suitable return and layout; a long connection can add parasitic impedance that defeats it.

Build the physical picture

Electromagnetic interference requires a source, coupling path and susceptible receiver. Conducted noise travels through shared impedance or cables; radiated coupling involves fields. Capacitive coupling responds to changing voltage, inductive coupling to changing current and loop geometry. Common-mode current on an external cable can radiate strongly even when differential signals look correct.

EMC includes emissions and immunity. A design that does not disturb other equipment can still fail during ESD or external RF exposure. Shielding, grounding and filtering need a defined current path; attaching a shield with a long inductive connection can undermine high-frequency performance.

From mechanism to a usable model

Begin with the coupling mechanism, then select mitigation. Reduce switching-loop area for magnetic coupling, control return paths, filter at the boundary where noise enters or leaves, and protect vulnerable interfaces. Validate under representative wiring and operating modes. A bench setup with a short cable can miss the failure seen in installation.

i_coupled=C_m·dv/dt; v_coupled=M·di/dt

Model assumptions: First-order coupling model; C_m and mutual inductance M depend on geometry.

Diagnose an interference problem

Change one source condition and check whether the disturbance follows it.

Identify whether noise arrives through power, signal, ground or field coupling.

Test a targeted mitigation and repeat the same measurement configuration.

Mistake to avoid: A ground symbol is not an equipotential physical conductor at all frequencies.

Worked problem: A 2 pF coupling capacitance sees a 3 V edge in 1 ns. Estimate injected current.

dv/dt=3×10⁹ V/s. i=2×10⁻¹²×3×10⁹=6 mA during the edge. Sensitive high-impedance nodes may respond even though the average current is tiny.

Self-test: Why can a cable increase emissions?

It can carry common-mode current and act as an efficient antenna compared with the compact board.

How does reducing a high-di/dt loop area help?

It generally reduces magnetic coupling and radiated disturbance from that loop. It does not automatically solve electric-field or cable common-mode coupling.

RF PCB design

A transmission line has a characteristic impedance defined by distributed capacitance and inductance. At an impedance discontinuity, part of an incident wave reflects. Controlled impedance depends on the full cross-section: width, copper thickness, reference spacing and dielectric properties.

At RF, component pads and vias also act as circuit elements. Match a load when the application needs power transfer or reflection control, and preserve the intended reference path. A 50 Ω trace is not a resistor consuming the signal’s power; it is the impedance of a travelling wave.

Build the physical picture

At RF, connectors, pads, vias and reference changes form a network of discontinuities. Microstrip and stripline confine fields differently, and effective permittivity differs from the bulk dielectric constant used in a simple capacitor calculation. The line’s phase and attenuation matter as well as its characteristic impedance.

S-parameters describe waves at defined reference planes and impedances. S11 is a reflected-wave ratio under the stated port conditions; S21 describes transmission. A measurement includes fixtures unless calibration or de-embedding moves the reference plane appropriately.

From mechanism to a usable model

Return loss is −20 log10|S11|, while mismatch loss depends on 1−|Γ|² in the simple case. Confusing these quantities can exaggerate the delivered-power loss. Frequency-dependent loss combines conductors, dielectric, radiation and mismatch; a longer cable or fixture can obscure a small board defect.

Γ=(Z_L−Z₀)/(Z_L+Z₀); propagation delay≈L√ε_eff/c

Model assumptions: Lossless line and real resistive load for the simple numerical example.

Read a basic RF measurement

State calibration plane, reference impedance and frequency range.

Convert a reflection magnitude into reflected power using |Γ|².

Separate mismatch from attenuation and inspect resonances or discontinuities against layout geometry.

Mistake to avoid: Large return loss in dB means small reflection, not large power loss.

Worked problem: A 50 Ω line ends in 100 Ω. Find voltage reflection coefficient.

Γ=(100−50)/(100+50)=1/3. One third of incident voltage amplitude reflects positively; reflected power fraction is |Γ|²=1/9 for this lossless reference.

Self-test: What happens for an open circuit and short circuit?

An ideal open has Γ=+1; an ideal short has Γ=−1. The signs describe reflected voltage polarity.

For |Γ|=0.1, find return loss and reflected-power fraction.

Return loss is 20 dB; reflected power is 0.01, or 1%. These are related but not numerically interchangeable.

Hybrid circuit technologies

Hybrid circuits integrate separately fabricated components and patterned conductors on a substrate. Thick-film processes often screen-print and fire conductor or resistor materials; thin-film processes use deposition and lithographic patterning. Their precision, thermal budgets and material properties differ.

Low-temperature co-fired ceramic (LTCC) stacks patterned ceramic green tapes, incorporates conductors and vias, and co-fires the assembly. Shrinkage and material compatibility require process control. Ceramic can support harsh or RF environments, but it introduces cost, mechanical and interconnect considerations.

Build the physical picture

Hybrid circuits combine components and patterned passive structures on substrates such as ceramics. Thick-film processing prints material pastes that are dried and fired according to their chemistry; thin-film processing deposits and patterns much thinner layers. The words describe process families, not simply arbitrary thickness categories.

Ceramic substrates can support thermal, dimensional or environmental requirements beyond ordinary laminates, but brittleness, cost and joining constraints remain. Printed resistors may be trimmed to adjust their value. Trimming geometry changes local current density and can affect noise and stability.

From mechanism to a usable model

A film resistor’s geometry gives R=Rs L/W for a uniform rectangular sheet away from contact effects. Sheet resistance has units Ω per square because scaling both dimensions leaves L/W unchanged. Geometry determines resistance, while material, temperature and process variation determine Rs.

R=R□ L/W

Model assumptions: Uniform planar resistor with negligible contact and end effects; R□ is sheet resistance in Ω/square.

Use sheet resistance correctly

Identify the patterned current path and its length-to-width ratio.

Multiply the number of squares by sheet resistance.

Account separately for contacts, bends and trimming changes if precision requires it.

Mistake to avoid: One square is a geometric ratio, not a fixed physical area.

Worked problem: A film has 100 Ω/square. A resistor is 2 mm long and 0.5 mm wide. Find resistance.

L/W=4 squares, so R=400 Ω. Doubling both dimensions preserves the number of squares and ideal resistance.

Self-test: Why must conductor material be compatible with LTCC firing?

The conductor and ceramic must survive the atmosphere and temperature while producing controlled shrinkage and adhesion.

A film with Rs=100 Ω/□ is 2 mm long and 0.5 mm wide. Find resistance.

It has four squares, giving 400 Ω. A 4 mm by 1 mm rectangle would have the same ideal value.

Packaging and reliability

Reliability asks whether function persists under a defined use history. Thermal-expansion mismatch loads joints during cycling; moisture can weaken interfaces or contribute to damage during heating. Delamination changes mechanical support and thermal paths. Electromigration moves atoms under electrical current and can create voids.

Accelerated testing must activate relevant mechanisms without substituting an unrelated failure. Failure analysis combines electrical symptoms with inspection and physical evidence. Separate initial yield, random failures and wear-out; one lifetime equation cannot explain every failure family.

Build the physical picture

Reliability asks whether the assembly keeps performing over a stated time and environment. Thermal cycling creates differential-expansion fatigue; moisture can drive corrosion or delamination; vibration loads joints and interconnects. Failure mechanisms differ, so one harsh test is not an all-purpose proof of lifetime.

Distinguish infant failures, random failures and wear-out. Screening can remove some initial defects without validating every aging mechanism. Accelerated tests need a physical link between stress and the field mechanism; excessive stress may activate a different mechanism and invalidate extrapolation.

From mechanism to a usable model

An Arrhenius rate model uses an activation energy and temperature to estimate acceleration for a thermally activated mechanism. Mechanical fatigue may require strain-range and cycling models instead. Record failures, censoring and sample size: zero observed failures is not a measured zero probability of failure.

AF=exp[(Eₐ/k)(1/T_use−1/T_test)]

Model assumptions: Arrhenius acceleration for one temperature-activated mechanism, constant activation energy and temperatures in kelvin.

Estimate a thermal acceleration factor

State the same assumed failure mechanism at use and test temperatures.

Convert both temperatures to kelvin.

Use AF=exp[(Ea/kB)(1/Tuse−1/Ttest)] and report the assumed activation energy rather than hiding it in a lifetime claim.

Mistake to avoid: A test passed by one prototype does not establish production reliability with high statistical confidence.

Worked problem: For Eₐ=0.7 eV, compare 85 °C use with 125 °C test.

T_use=358.15 K, T_test=398.15 K and k=8.617×10⁻⁵ eV/K. AF≈exp(2.279)=9.76. A model is valid only if the same mechanism governs both conditions.

Self-test: Why is “1000 hours tested” insufficient as a reliability claim?

Stress conditions, failure criteria, sample count, mechanism and statistical confidence are required.

Why might a much hotter test give a misleading lifetime prediction?

It can change materials or activate a new mechanism, such as a different chemical reaction or softening process, violating the assumed acceleration model.

Advanced system integration

System-in-package places multiple dies and components in one package; heterogeneous integration combines technologies selected for different functions. Short interconnects can reduce parasitics, but power delivery, heat removal, testing and repair become harder. Yield across multiple components also matters.

A monolithic system integrates functions on one die, while multichip approaches allow different processes for logic, memory, sensors or RF. Choose the architecture by interface needs and manufacturing economics. More integration does not automatically improve thermal behaviour or test coverage.

Build the physical picture

Advanced integration shortens electrical connections by combining dies, interposers, packages and boards. Chiplets partition functions across multiple dies; an interposer supplies dense routing; through-silicon vias provide vertical connectivity in selected structures. Each partition trades yield, test access, bandwidth, power and heat removal.

Shorter connections can reduce parasitic delay and energy, but stacking can make heat extraction harder. Mechanical stress and power delivery become tightly coupled with signal performance. “More integrated” does not mean every design constraint improves.

From mechanism to a usable model

Known-good-die testing aims to avoid assembling costly systems around defective dies, but some failures appear only after integration. System-level test must therefore include interconnect, thermal and communication behaviour. Packaging boundaries also define ownership of interface specifications and debug access.

Assembly yield≈∏Yᵢ × Y_interconnect

Model assumptions: Independent yields and no repair, screening or correlated failures; an illustrative first estimate.

Evaluate an integration proposal

Compare electrical link length and required data rate with the current design.

Trace the heat and power paths through the proposed stack.

Include yield, repair/test strategy and assembly tolerances in the decision rather than comparing density alone.

Mistake to avoid: Stacking dies is not equivalent to adding circuit layers to an ordinary PCB.

Worked problem: Four dies each have 98% yield and interconnection yield is 99%. Estimate unscreened assembly yield.

0.98⁴×0.99≈0.913, or 91.3%. Known-good-die screening can improve final yield but adds test cost and still has escape risks.

Self-test: What trade-off arises when stacking dies?

Interconnect length can fall while internal heat paths and inspection access become less favourable.

Why can a shorter high-bandwidth link still produce a worse system?

It may improve signal performance while concentrating heat, complicating power delivery or reducing testability and yield. A system decision needs all these budgets.

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