Interrupt Foundations
Interrupt entry, priority, latency, shared state and bounded interrupt handlers.
Interactive lab
This page is a live simulation rather than a written lesson: enable JavaScript to use its controls, visualizations, and code traces. The written lessons for this subject are linked below.
More in Foundations
- Pointers & Memory SafetyAddresses, dereferencing, arrays, pointer arithmetic, ownership and invalid accesses.
- How a Computer WorksCPU, memory, storage, buses, instructions and the performance of the complete system.
- Cache CoherencyMESI, ownership, ordering, atomics, DMA and false sharing.
- Linkers & Build SystemsTranslation, symbols, linker scripts, sections, map files and reproducible builds.
- Number RepresentationBinary, hexadecimal, signed values, two's complement and representation limits.
- Connect & Debug a BoardPower, ground, SWD, target voltage and a systematic first-connection diagnosis.
- Bit ManipulationMasks, shifts, bit fields, set, clear and toggle operations with boundary cases.
- Byte Order & EndiannessByte order in memory, wire formats and portable byte-wise decoding.
- Start Here & Boot OverviewFollow the learning path and the timeline from power-on to main().
- Cache MappingCache lines, tags, sets, associativity, replacement and locality.
- Memory, Stack & HeapStorage regions, allocation, stack growth, lifetime and memory exhaustion.
- MCU StartupReset vectors, initial stack, copying data, clearing bss and entering main().