Logic Levels & Interfacing

Logic Levels and Families: What a 1 Is in Volts

A logic level is a range of voltages, not a value, and an interface between two parts works only if the driver's guaranteed output ranges fall inside the receiver's accepted input ranges. Four numbers define that: VOH and VOL from the driver, VIH and VIL at the receiver. The gaps between them are the noise margin - how much interference a signal can pick up and still be read correctly - and the most common interfacing mistake comes from one asymmetry between TTL and CMOS thresholds.

How it is built

• VOH is the lowest voltage a driver guarantees for a high output and VOL the highest for a low. Both are worst-case over temperature, supply and load, which is why they are not simply the rails.
• VIH is the lowest voltage a receiver guarantees to read as high and VIL the highest it reads as low. Between them is an undefined region where the input may read either way, and a signal lingering there can oscillate.
• High noise margin is VOH minus VIH, and low noise margin is VIL minus VOL. Both must be positive for the interface to work, and the smaller of the two is the one noise has to overcome.
• TTL thresholds are historic - 2.0 V for a high, 0.8 V for a low - and every later family stayed compatible with them, which is why a 3.3 V output drives a 5 V TTL input comfortably.
• CMOS thresholds scale with the supply, typically 70% and 30% of it. A 5 V CMOS input needs 3.5 V for a high, which a 3.3 V driver cannot supply - the same driver that works into 5 V TTL fails into 5 V CMOS.
• Over-voltage is a separate concern from thresholds. Driving 5 V into a 1.8 V input conducts through the protection diode regardless of whether the levels would otherwise be compatible, and needs a level shifter or at minimum a series resistor.

Design procedure

1. Write down all four numbers for both parts from their datasheets rather than assuming from the supply voltage.
2. Compute both noise margins. A negative one means the interface does not work, however well it appears to behave on the bench.
3. Check for over-voltage separately: is the driver's high above the receiver's absolute maximum, and is the input specified as tolerant?
4. Distinguish TTL from CMOS thresholds when a datasheet says a supply voltage. 'Five volt' says nothing about which thresholds apply.
5. For a marginal interface, use a proper level shifter rather than a resistor divider on anything fast - the divider plus input capacitance is a low-pass filter.
6. Verify with a scope at the receiver's pin rather than the driver's, since the level after the trace and the load is what actually matters.

Key terms

VOH / VOL

Driver's guaranteed high and low output levels, worst case.

VIH / VIL

Receiver's thresholds for reading a high and a low.

Noise margin

VOH-VIH and VIL-VOL. Both must be positive.

Undefined region

Between VIL and VIH. A signal lingering here can oscillate.

TTL thresholds

2.0 V and 0.8 V, independent of supply. Historic and still standard.

CMOS thresholds

About 70% and 30% of supply. Scale with the rail.

5 V tolerant

An input that survives 5 V. Says nothing about whether levels work.

Level shifter

A part that translates levels properly. Preferable to a divider above low speeds.

Worked example

A 3.3 V microcontroller drives two 5 V parts. The first has TTL-compatible inputs with a VIH of 2.0 V, so the 3.0 V output has a full volt of margin and works. The second is 5 V CMOS with a VIH of 3.5 V, so the same 3.0 V output is below the threshold - it may read correctly at room temperature on a good day and fail as the part warms. Same driver, same trace, same supply: the difference is one number in the receiver's datasheet, and only reading it distinguishes the two cases.

Common pitfalls

Digital Power: Dynamic, Short-Circuit and Leakage

A CMOS circuit consumes power in three ways, and which one dominates decides entirely which technique is worth applying. Dynamic power charges and discharges load capacitance every time a node switches, and is proportional to activity, capacitance, frequency and the square of the supply voltage. Short-circuit power flows during the transition while both networks briefly conduct. Leakage flows continuously whether or not anything is switching, and it is the term that has grown with every process generation.

How it is built

• Dynamic power is alpha times C times V squared times f. Every node switching charges its load capacitance from the supply and then dumps that charge to ground, so the energy per transition is proportional to CV squared.
• The square on voltage is the single most important fact in low-power design. A 20% supply reduction removes 36% of the dynamic power, while a 20% frequency reduction removes only 20%.
• Short-circuit power flows during a transition, when the input is midway and both networks conduct briefly. It is typically a few percent of dynamic power and grows sharply with slow input edges, which is one reason slew rate matters.
• Leakage is subthreshold conduction plus gate tunnelling, and it flows with the clock stopped. It roughly doubles for every 10 degrees of junction temperature, so a hot part leaks dramatically more than a cool one.
• Clock gating attacks the activity factor by stopping the clock to blocks that have nothing to do. It removes their dynamic power entirely and does nothing about leakage.
• Power gating removes the supply, which is the only technique that stops leakage. It costs wake-up time and loses state, which is why it is used at coarse granularity and clock gating at fine.

Design procedure

1. Compute all three terms for the actual operating point before choosing a technique. The dominant one is usually not the one assumed.
2. If dynamic power dominates, attack voltage first because of the square, then activity through clock gating, then frequency.
3. If leakage dominates - which it does at idle, at high temperature, or on a fine process - only power gating helps, and clock gating changes nothing at all.
4. Use dynamic voltage and frequency scaling together: a lower voltage supports a lower maximum frequency, so the two are lowered as a pair and the saving is more than either alone.
5. Keep input edges fast to limit short-circuit current, which means paying attention to fan-out and drive strength on slow nets.
6. Measure at the actual junction temperature. A leakage figure quoted at 25 degrees understates a part running at 85 by a factor of about sixty.

Key terms

Dynamic power

alpha C V^2 f. Charging and discharging load capacitance.

Activity factor (alpha)

Fraction of nodes switching per clock. Typically 0.1 to 0.2.

Short-circuit power

Both networks conducting during a transition. Worse with slow edges.

Leakage

Subthreshold and gate current. Flows with the clock stopped.

Clock gating

Stopping the clock to idle blocks. Attacks activity, not leakage.

Power gating

Removing the supply. The only technique that stops leakage.

DVFS

Lowering voltage and frequency together, since one bounds the other.

Temperature doubling

Leakage roughly doubles every 10 degrees of junction temperature.

Worked example

A design switching 500 pF at 3.3 V and 50 MHz with an activity factor of 0.15 dissipates about 41 mW dynamically, against roughly 0.17 mW of leakage at room temperature - dynamic dominates completely and clock gating is the obvious lever. Stop the clock and dynamic power goes to zero, leaving leakage as the entire budget. Now raise the junction to 85 degrees: leakage is sixty times larger, around 10 mW, in a part that is doing nothing at all. That is why a battery device that sleeps well at room temperature can have a disappointing standby life in a warm enclosure.

Common pitfalls

Logic levels, thresholds and noise margin

A logic family is defined by four voltages: the highest level a driver guarantees as a 0, the lowest it guarantees as a 1, and the two thresholds a receiver uses to decide. Noise margin is the gap between what the driver promises and what the receiver requires, and it is the entire reason digital signalling is robust. When two families are connected without checking these four numbers, the link either works by luck or fails intermittently.

How it is built

• V_OL and V_OH are what a driver guarantees under specified load; V_IL and V_IH are what a receiver requires.
• High-level noise margin is V_OH minus V_IH; low-level is V_IL minus V_OL. Both must be positive for the link to be valid.
• The region between V_IL and V_IH is undefined: a receiver may read either value, and two receivers may disagree.
• TTL thresholds are fixed near 0.8 V and 2.0 V; CMOS thresholds scale with supply, typically 30% and 70% of V_DD.
• A 3.3 V CMOS driver into a 5 V CMOS receiver is the classic failure: V_OH of 3.3 V does not reach a V_IH of 3.5 V, so the link has negative margin and works only by chance.

Design procedure

1. Write down all four voltages from both datasheets before connecting parts from different families.
2. Compute both noise margins and require both positive with a real margin, not merely non-negative.
3. Use a level shifter wherever the margin is negative, rather than hoping the typical case holds across temperature.
4. Check whether the receiver is 5 V tolerant before driving it above its own supply; tolerance is a specific feature, not an assumption.
5. Use a Schmitt-trigger input for any slow or noisy edge, since a slow transit through the undefined region can produce multiple output transitions.

Key terms

V_OH / V_OL

Output high and low voltages a driver guarantees under load.

V_IH / V_IL

Input thresholds a receiver requires to read a 1 or a 0 reliably.

Noise margin

The gap between guaranteed drive and required threshold. Must be positive on both rails.

5 V tolerant

An input that accepts voltages above its own supply without damage. A specified feature.

Hysteresis

Different rising and falling thresholds, so a noisy or slow edge still produces one clean transition.

Worked example

The four numbers, and the connection that fails:

  3.3 V LVCMOS driver     V_OH = 2.9 V min,  V_OL = 0.4 V max
  5 V CMOS receiver       V_IH = 3.5 V min,  V_IL = 1.5 V max

    high margin = V_OH - V_IH = 2.9 - 3.5 = -0.6 V    NEGATIVE
    low  margin = V_IL - V_OL = 1.5 - 0.4 = +1.1 V    fine

  The driver cannot reach the receiver's threshold for a 1. It may
  work on the bench at room temperature and fail cold, or work on
  one board and not the next - the signature of a link that has no
  margin rather than one that is broken.

  Same driver into a 5 V TTL receiver:

    V_IH = 2.0 V,  high margin = 2.9 - 2.0 = +0.9 V   fine

  TTL thresholds are low enough that 3.3 V CMOS drives them
  directly, which is why the same driver works with one 5 V part
  and not another. The family matters, not the supply voltage.

Common pitfalls

Drive strength, fan-out and open-drain

An output can only source and sink a finite current, and every input it drives takes some. Fan-out is how many inputs one output can drive while still meeting its guaranteed levels, and exceeding it does not fail cleanly - the levels degrade, the noise margin shrinks, and the edges slow until something misreads. Open-drain outputs invert the problem: they can only pull low, which is what makes them shareable.

How it is built

• A push-pull output actively drives both high and low, so two of them fighting on one net is a short circuit through both drivers.
• An open-drain output pulls low only, and relies on an external resistor to pull high, so several may share a net safely.
• The pull-up resistor sets a trade: smaller means faster rising edges and more current; larger means slower edges and less power.
• The rising edge is an RC exponential with R the pull-up and C the total bus capacitance, which is what limits I2C speed.
• CMOS input current is negligible, so DC fan-out is large and capacitive loading is the real constraint - every input adds capacitance and slows every edge.

Design procedure

1. Add up the capacitance of every input on a net plus the trace, and check the resulting edge rate against what the receivers need.
2. Size a pull-up from the required rise time and the bus capacitance, then confirm the driver can sink the resulting current at its V_OL.
3. Use open-drain for any shared bus, any level shift downward, and any wired-AND such as an interrupt line from several devices.
4. Never connect two push-pull outputs to the same net, and check that a bidirectional pin's direction control cannot enable both ends.
5. Add a buffer where fan-out is genuinely exceeded, rather than accepting degraded levels.

Key terms

Fan-out

How many inputs one output can drive within its guaranteed levels.

Push-pull

An output that actively drives both directions. Fast, cannot be shared.

Open drain

An output that pulls low only. Shareable, needs an external pull-up.

Wired-AND

Several open-drain outputs on one net: the net is high only if all release it.

RC rise time

The pull-up resistance times the bus capacitance. What limits an open-drain bus's speed.

Worked example

Sizing an I2C pull-up, which is the everyday version of this:

  bus capacitance   100 pF   (traces plus every device on the bus)
  target rise time  300 ns   (I2C fast mode limit)

  t_rise is about 0.85 x R x C for the 30%-70% transition

    R = 300 ns / (0.85 x 100 pF) = about 3.5 kohm maximum

  and the lower bound comes from the driver:

    3.3 V / 3 mA sink at V_OL = about 1.1 kohm minimum

  So anywhere from 1.1 k to 3.5 k works; 2.2 k is the common
  choice. Adding devices raises C, which lowers the maximum R -
  which is why a bus that worked with four devices can fail when
  the fifth is added and nothing else changed.

And the wired-AND that makes shared interrupt lines work:

  three open-drain outputs, one pull-up
  net is HIGH only when all three release
  any one pulling low takes the net low, with no contention

Common pitfalls

Where the power actually goes

A CMOS gate draws almost no current holding a value and a large current changing one, so digital power is dominated by switching rather than by state. That makes dynamic power proportional to activity, capacitance, frequency and the square of the supply voltage - and the square is why voltage scaling has always been the most effective lever available. Static power was negligible for decades and stopped being so as leakage grew with each process node.

How it is built

• Dynamic power is roughly alpha x C x V^2 x f: activity factor, switched capacitance, supply squared, frequency.
• The V^2 term means halving the supply quarters dynamic power, which is why dynamic voltage scaling exists and why it beats frequency scaling.
• Short-circuit power is drawn during a transition while both the pull-up and pull-down networks conduct briefly; slow edges make it worse.
• Static power is leakage: subthreshold conduction and gate leakage, present whenever the part is powered and growing as thresholds fall.
• Clock gating removes the activity factor for an idle block and is usually the largest single dynamic saving available.

Design procedure

1. Reduce the supply voltage first where the design allows it; nothing else has a squared term.
2. Gate clocks to idle blocks, using the flip-flop's clock enable rather than a gate in the clock path.
3. Reduce switched capacitance by keeping high-activity nets short and off long traces.
4. Keep edges fast enough to limit short-circuit current, which trades against the noise a fast edge produces.
5. Measure rather than model: activity factor is workload-dependent and is the term hardest to predict.

Key terms

Dynamic power

Power drawn switching. alpha x C x V^2 x f, and the dominant term in active logic.

Activity factor

The fraction of clock cycles a net actually toggles. Workload-dependent.

Short-circuit power

Current flowing through both networks during a transition. Worsens with slow edges.

Leakage

Static current present whenever powered. Negligible historically, significant at modern nodes.

Clock gating

Stopping the clock to an idle block, zeroing its activity factor.

Worked example

Why voltage is the lever, and clock gating is the easy win:

  P_dyn = alpha x C x V^2 x f

  baseline        1.8 V, 100 MHz          ->  1.00 (normalised)
  halve frequency 1.8 V,  50 MHz          ->  0.50
  drop voltage    1.2 V, 100 MHz          ->  0.44
  both            1.2 V,  50 MHz          ->  0.22

  Dropping the supply by a third beats halving the clock, because
  the voltage term is squared and the frequency term is not. The
  catch is that a lower supply means slower logic, so the two are
  coupled - which is exactly what dynamic voltage and frequency
  scaling manages.

  And the activity term, which costs nothing to exploit:

    a block clocked but idle    alpha is still high - every
                                flip-flop toggles its clock input
    the same block gated        alpha goes to zero

  Clock gating an idle peripheral is usually a larger saving than
  any amount of logic optimisation inside it.

Common pitfalls

GPIO: Every Stage Between a Register Bit and a Pin

Writing a bit does not move a pin. Between the register and the package there is a clock gate, a mode selection, an output driver, a pull resistor network, a slew-rate control and often an alternate-function multiplexer - and a pin that will not move is stuck at one of them. Knowing the stages turns an open-ended problem into a checklist that is six items long.

How it is built

• The peripheral clock must be enabled before any of the port's registers respond. Without it every write is discarded and every read returns zero.
• Mode selects whether the pin is an input, an output, an analog input or an alternate function. A pin left in its reset mode - usually analog or high-impedance input - will not drive regardless of what is written to the output register.
• The alternate-function multiplexer routes a peripheral's signal to the pin. A UART's transmit line only reaches the package if the pin is in alternate mode and the correct function number is selected, and those numbers are per-pin.
• Output type is push-pull or open-drain. Push-pull drives both directions; open-drain only pulls low and needs a pull-up, which is what I2C and any shared line requires.
• Pull-up and pull-down resistors define the level when nothing drives the pin. An input with neither floats, and a floating CMOS input reads randomly and draws current.
• Slew-rate and drive-strength settings trade edge speed against emissions and ringing. The fastest setting is not the best default; it is the one that produces overshoot on a long trace.

Design procedure

1. Enable the port's clock first, and read back a register to confirm it took.
2. Set the mode, then verify by reading the mode register rather than assuming the write landed.
3. For a peripheral function, set alternate mode and the correct function number for that specific pin - the mapping differs per pin and the datasheet table is the authority.
4. Choose push-pull or open-drain from what the net requires, and add a pull-up for any open-drain output.
5. Configure pulls on every input, including unused pins. A floating input is both a random read and a source of leakage current.
6. Probe the pin with a scope when it does not behave. A pin sitting at half the supply is floating; one stuck low may be configured as an input with a pull-down while the code writes the output register.

Key terms

Peripheral clock enable

Gates the port's registers. First stage, and the usual failure.

Mode register

Input, output, analog or alternate function.

Alternate function

Routes a peripheral signal to the pin. Numbering is per pin.

Push-pull

Drives both high and low.

Open-drain

Pulls low only. Needs a pull-up, and allows shared lines.

Pull-up / pull-down

Defines the level when nothing drives. Required on every input.

Slew rate

Edge speed. Faster is not better - it causes overshoot and emissions.

Floating input

Undriven CMOS input. Reads randomly and draws current.

Worked example

A UART transmits nothing. The peripheral is configured, the clock is enabled, the baud rate is right, and the transmit register accepts data. The pin is still in its reset mode - a high-impedance input - so the UART's output never reaches the package. Setting alternate mode and the correct function number for that pin fixes it in two register writes. A scope on the pin would have shown it floating rather than idling high, which distinguishes this from every UART configuration problem in one measurement.

Common pitfalls

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